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net/axgbe: support unicast hash table for MAC address
[dpdk.git]
/
drivers
/
net
/
axgbe
/
axgbe_common.h
diff --git
a/drivers/net/axgbe/axgbe_common.h
b/drivers/net/axgbe/axgbe_common.h
index
298e794
..
7abab60
100644
(file)
--- a/
drivers/net/axgbe/axgbe_common.h
+++ b/
drivers/net/axgbe/axgbe_common.h
@@
-34,7
+34,6
@@
#include <rte_ethdev.h>
#include <rte_dev.h>
#include <rte_errno.h>
#include <rte_ethdev.h>
#include <rte_dev.h>
#include <rte_errno.h>
-#include <rte_dev.h>
#include <rte_ethdev_pci.h>
#include <rte_common.h>
#include <rte_cycles.h>
#include <rte_ethdev_pci.h>
#include <rte_common.h>
#include <rte_cycles.h>
@@
-290,6
+289,11
@@
#define MAC_RQC2_INC 4
#define MAC_RQC2_Q_PER_REG 4
#define MAC_RQC2_INC 4
#define MAC_RQC2_Q_PER_REG 4
+#define MAC_MACAHR(i) (MAC_MACA0HR + ((i) * 8))
+#define MAC_MACALR(i) (MAC_MACA0LR + ((i) * 8))
+
+#define MAC_HTR(i) (MAC_HTR0 + ((i) * MAC_HTR_INC))
+
/* MAC register entry bit positions and sizes */
#define MAC_HWF0R_ADDMACADRSEL_INDEX 18
#define MAC_HWF0R_ADDMACADRSEL_WIDTH 5
/* MAC register entry bit positions and sizes */
#define MAC_HWF0R_ADDMACADRSEL_INDEX 18
#define MAC_HWF0R_ADDMACADRSEL_WIDTH 5
@@
-842,6
+846,8
@@
#define PCS_V1_WINDOW_SELECT 0x03fc
#define PCS_V2_WINDOW_DEF 0x9060
#define PCS_V2_WINDOW_SELECT 0x9064
#define PCS_V1_WINDOW_SELECT 0x03fc
#define PCS_V2_WINDOW_DEF 0x9060
#define PCS_V2_WINDOW_SELECT 0x9064
+#define PCS_V2_RV_WINDOW_DEF 0x1060
+#define PCS_V2_RV_WINDOW_SELECT 0x1064
/* PCS register entry bit positions and sizes */
#define PCS_V2_WINDOW_DEF_OFFSET_INDEX 6
/* PCS register entry bit positions and sizes */
#define PCS_V2_WINDOW_DEF_OFFSET_INDEX 6
@@
-1134,6
+1140,8
@@
#define RX_NORMAL_DESC3_PL_WIDTH 14
#define RX_NORMAL_DESC3_RSV_INDEX 26
#define RX_NORMAL_DESC3_RSV_WIDTH 1
#define RX_NORMAL_DESC3_PL_WIDTH 14
#define RX_NORMAL_DESC3_RSV_INDEX 26
#define RX_NORMAL_DESC3_RSV_WIDTH 1
+#define RX_NORMAL_DESC3_LD_INDEX 28
+#define RX_NORMAL_DESC3_LD_WIDTH 1
#define RX_DESC3_L34T_IPV4_TCP 1
#define RX_DESC3_L34T_IPV4_UDP 2
#define RX_DESC3_L34T_IPV4_TCP 1
#define RX_DESC3_L34T_IPV4_UDP 2
@@
-1247,6
+1255,10
@@
#define MDIO_VEND2_AN_STAT 0x8002
#endif
#define MDIO_VEND2_AN_STAT 0x8002
#endif
+#ifndef MDIO_VEND2_PMA_CDR_CONTROL
+#define MDIO_VEND2_PMA_CDR_CONTROL 0x8056
+#endif
+
#ifndef MDIO_CTRL1_SPEED1G
#define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
#endif
#ifndef MDIO_CTRL1_SPEED1G
#define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
#endif
@@
-1293,6
+1305,11
@@
#define AXGBE_AN_CL37_PCS_MODE_BASEX 0x00
#define AXGBE_AN_CL37_PCS_MODE_SGMII 0x04
#define AXGBE_AN_CL37_TX_CONFIG_MASK 0x08
#define AXGBE_AN_CL37_PCS_MODE_BASEX 0x00
#define AXGBE_AN_CL37_PCS_MODE_SGMII 0x04
#define AXGBE_AN_CL37_TX_CONFIG_MASK 0x08
+#define AXGBE_AN_CL37_MII_CTRL_8BIT 0x0100
+
+#define AXGBE_PMA_CDR_TRACK_EN_MASK 0x01
+#define AXGBE_PMA_CDR_TRACK_EN_OFF 0x00
+#define AXGBE_PMA_CDR_TRACK_EN_ON 0x01
/*generic*/
#define __iomem
/*generic*/
#define __iomem
@@
-1344,9
+1361,9
@@
do { \
#define SET_BITS_LE(_var, _index, _width, _val) \
do { \
#define SET_BITS_LE(_var, _index, _width, _val) \
do { \
- (_var) &= rte_cpu_to_le_32(~(((0x1 << (_width)) - 1) << (_index)));\
+ (_var) &= rte_cpu_to_le_32(~(((0x1
U
<< (_width)) - 1) << (_index)));\
(_var) |= rte_cpu_to_le_32((((_val) & \
(_var) |= rte_cpu_to_le_32((((_val) & \
- ((0x1
<< (_width)) - 1)) << (_index)));
\
+ ((0x1
U << (_width)) - 1)) << (_index)));
\
} while (0)
/* Bit setting and getting macros based on register fields
} while (0)
/* Bit setting and getting macros based on register fields
@@
-1385,7
+1402,7
@@
do { \
* register definitions formed using the input names
*/
#define AXGMAC_IOREAD(_pdata, _reg) \
* register definitions formed using the input names
*/
#define AXGMAC_IOREAD(_pdata, _reg) \
- rte_read32((
void *)((_pdata)->xgmac_regs + (_reg)
))
+ rte_read32((
uint8_t *)((_pdata)->xgmac_regs) + (_reg
))
#define AXGMAC_IOREAD_BITS(_pdata, _reg, _field) \
GET_BITS(AXGMAC_IOREAD((_pdata), _reg), \
#define AXGMAC_IOREAD_BITS(_pdata, _reg, _field) \
GET_BITS(AXGMAC_IOREAD((_pdata), _reg), \
@@
-1393,7
+1410,8
@@
do { \
_reg##_##_field##_WIDTH)
#define AXGMAC_IOWRITE(_pdata, _reg, _val) \
_reg##_##_field##_WIDTH)
#define AXGMAC_IOWRITE(_pdata, _reg, _val) \
- rte_write32((_val), (void *)((_pdata)->xgmac_regs + (_reg)))
+ rte_write32((_val), \
+ (uint8_t *)((_pdata)->xgmac_regs) + (_reg))
#define AXGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \
do { \
#define AXGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \
do { \
@@
-1409,8
+1427,8
@@
do { \
* base register value is calculated by the queue or traffic class number
*/
#define AXGMAC_MTL_IOREAD(_pdata, _n, _reg) \
* base register value is calculated by the queue or traffic class number
*/
#define AXGMAC_MTL_IOREAD(_pdata, _n, _reg) \
- rte_read32((
void *)((_pdata)->xgmac_regs +
\
- MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg))
)
+ rte_read32((
uint8_t *)((_pdata)->xgmac_regs) +
\
+ MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg))
#define AXGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \
GET_BITS(AXGMAC_MTL_IOREAD((_pdata), (_n), (_reg)), \
#define AXGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \
GET_BITS(AXGMAC_MTL_IOREAD((_pdata), (_n), (_reg)), \
@@
-1418,8
+1436,8
@@
do { \
_reg##_##_field##_WIDTH)
#define AXGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \
_reg##_##_field##_WIDTH)
#define AXGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \
- rte_write32((_val), (
void *)((_pdata)->xgmac_regs +
\
- MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg))
)
+ rte_write32((_val), (
uint8_t *)((_pdata)->xgmac_regs) +
\
+ MTL_Q_BASE + ((_n) * MTL_Q_INC) + (_reg))
#define AXGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \
do { \
#define AXGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \
do { \
@@
-1435,7
+1453,7
@@
do { \
* base register value is obtained from the ring
*/
#define AXGMAC_DMA_IOREAD(_channel, _reg) \
* base register value is obtained from the ring
*/
#define AXGMAC_DMA_IOREAD(_channel, _reg) \
- rte_read32((
void *)((_channel)->dma_regs + (_reg)
))
+ rte_read32((
uint8_t *)((_channel)->dma_regs) + (_reg
))
#define AXGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \
GET_BITS(AXGMAC_DMA_IOREAD((_channel), _reg), \
#define AXGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \
GET_BITS(AXGMAC_DMA_IOREAD((_channel), _reg), \
@@
-1443,7
+1461,8
@@
do { \
_reg##_##_field##_WIDTH)
#define AXGMAC_DMA_IOWRITE(_channel, _reg, _val) \
_reg##_##_field##_WIDTH)
#define AXGMAC_DMA_IOWRITE(_channel, _reg, _val) \
- rte_write32((_val), (void *)((_channel)->dma_regs + (_reg)))
+ rte_write32((_val), \
+ (uint8_t *)((_channel)->dma_regs) + (_reg))
#define AXGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \
do { \
#define AXGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \
do { \
@@
-1468,16
+1487,18
@@
do { \
_prefix##_##_field##_WIDTH, (_val))
#define XPCS32_IOWRITE(_pdata, _off, _val) \
_prefix##_##_field##_WIDTH, (_val))
#define XPCS32_IOWRITE(_pdata, _off, _val) \
- rte_write32(_val, (void *)((_pdata)->xpcs_regs + (_off)))
+ rte_write32(_val, \
+ (uint8_t *)((_pdata)->xpcs_regs) + (_off))
#define XPCS32_IOREAD(_pdata, _off) \
#define XPCS32_IOREAD(_pdata, _off) \
- rte_read32((
void *)((_pdata)->xpcs_regs + (_off)
))
+ rte_read32((
uint8_t *)((_pdata)->xpcs_regs) + (_off
))
#define XPCS16_IOWRITE(_pdata, _off, _val) \
#define XPCS16_IOWRITE(_pdata, _off, _val) \
- rte_write16(_val, (void *)((_pdata)->xpcs_regs + (_off)))
+ rte_write16(_val, \
+ (uint8_t *)((_pdata)->xpcs_regs) + (_off))
#define XPCS16_IOREAD(_pdata, _off) \
#define XPCS16_IOREAD(_pdata, _off) \
- rte_read16((
void *)((_pdata)->xpcs_regs + (_off)
))
+ rte_read16((
uint8_t *)((_pdata)->xpcs_regs) + (_off
))
/* Macros for building, reading or writing register values or bits
* within the register values of SerDes integration registers.
/* Macros for building, reading or writing register values or bits
* within the register values of SerDes integration registers.
@@
-1493,7
+1514,7
@@
do { \
_prefix##_##_field##_WIDTH, (_val))
#define XSIR0_IOREAD(_pdata, _reg) \
_prefix##_##_field##_WIDTH, (_val))
#define XSIR0_IOREAD(_pdata, _reg) \
- rte_read16((
void *)((_pdata)->sir0_regs + (_reg)
))
+ rte_read16((
uint8_t *)((_pdata)->sir0_regs) + (_reg
))
#define XSIR0_IOREAD_BITS(_pdata, _reg, _field) \
GET_BITS(XSIR0_IOREAD((_pdata), _reg), \
#define XSIR0_IOREAD_BITS(_pdata, _reg, _field) \
GET_BITS(XSIR0_IOREAD((_pdata), _reg), \
@@
-1501,7
+1522,8
@@
do { \
_reg##_##_field##_WIDTH)
#define XSIR0_IOWRITE(_pdata, _reg, _val) \
_reg##_##_field##_WIDTH)
#define XSIR0_IOWRITE(_pdata, _reg, _val) \
- rte_write16((_val), (void *)((_pdata)->sir0_regs + (_reg)))
+ rte_write16((_val), \
+ (uint8_t *)((_pdata)->sir0_regs) + (_reg))
#define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \
do { \
#define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \
do { \
@@
-1513,7
+1535,7
@@
do { \
} while (0)
#define XSIR1_IOREAD(_pdata, _reg) \
} while (0)
#define XSIR1_IOREAD(_pdata, _reg) \
- rte_read16((
void *)((_pdata)->sir1_regs + _reg)
)
+ rte_read16((
uint8_t *)((_pdata)->sir1_regs) + _reg
)
#define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \
GET_BITS(XSIR1_IOREAD((_pdata), _reg), \
#define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \
GET_BITS(XSIR1_IOREAD((_pdata), _reg), \
@@
-1521,7
+1543,8
@@
do { \
_reg##_##_field##_WIDTH)
#define XSIR1_IOWRITE(_pdata, _reg, _val) \
_reg##_##_field##_WIDTH)
#define XSIR1_IOWRITE(_pdata, _reg, _val) \
- rte_write16((_val), (void *)((_pdata)->sir1_regs + (_reg)))
+ rte_write16((_val), \
+ (uint8_t *)((_pdata)->sir1_regs) + (_reg))
#define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \
do { \
#define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \
do { \
@@
-1536,7
+1559,7
@@
do { \
* within the register values of SerDes RxTx registers.
*/
#define XRXTX_IOREAD(_pdata, _reg) \
* within the register values of SerDes RxTx registers.
*/
#define XRXTX_IOREAD(_pdata, _reg) \
- rte_read16((
void *)((_pdata)->rxtx_regs + (_reg)
))
+ rte_read16((
uint8_t *)((_pdata)->rxtx_regs) + (_reg
))
#define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \
GET_BITS(XRXTX_IOREAD((_pdata), _reg), \
#define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \
GET_BITS(XRXTX_IOREAD((_pdata), _reg), \
@@
-1544,7
+1567,8
@@
do { \
_reg##_##_field##_WIDTH)
#define XRXTX_IOWRITE(_pdata, _reg, _val) \
_reg##_##_field##_WIDTH)
#define XRXTX_IOWRITE(_pdata, _reg, _val) \
- rte_write16((_val), (void *)((_pdata)->rxtx_regs + (_reg)))
+ rte_write16((_val), \
+ (uint8_t *)((_pdata)->rxtx_regs) + (_reg))
#define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \
do { \
#define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \
do { \
@@
-1569,7
+1593,7
@@
do { \
_prefix##_##_field##_WIDTH, (_val))
#define XP_IOREAD(_pdata, _reg) \
_prefix##_##_field##_WIDTH, (_val))
#define XP_IOREAD(_pdata, _reg) \
- rte_read32((
void *)((_pdata)->xprop_regs + (_reg)
))
+ rte_read32((
uint8_t *)((_pdata)->xprop_regs) + (_reg
))
#define XP_IOREAD_BITS(_pdata, _reg, _field) \
GET_BITS(XP_IOREAD((_pdata), (_reg)), \
#define XP_IOREAD_BITS(_pdata, _reg, _field) \
GET_BITS(XP_IOREAD((_pdata), (_reg)), \
@@
-1577,7
+1601,8
@@
do { \
_reg##_##_field##_WIDTH)
#define XP_IOWRITE(_pdata, _reg, _val) \
_reg##_##_field##_WIDTH)
#define XP_IOWRITE(_pdata, _reg, _val) \
- rte_write32((_val), (void *)((_pdata)->xprop_regs + (_reg)))
+ rte_write32((_val), \
+ (uint8_t *)((_pdata)->xprop_regs) + (_reg))
#define XP_IOWRITE_BITS(_pdata, _reg, _field, _val) \
do { \
#define XP_IOWRITE_BITS(_pdata, _reg, _field, _val) \
do { \
@@
-1602,7
+1627,7
@@
do { \
_prefix##_##_field##_WIDTH, (_val))
#define XI2C_IOREAD(_pdata, _reg) \
_prefix##_##_field##_WIDTH, (_val))
#define XI2C_IOREAD(_pdata, _reg) \
- rte_read32((
void *)((_pdata)->xi2c_regs + (_reg)
))
+ rte_read32((
uint8_t *)((_pdata)->xi2c_regs) + (_reg
))
#define XI2C_IOREAD_BITS(_pdata, _reg, _field) \
GET_BITS(XI2C_IOREAD((_pdata), (_reg)), \
#define XI2C_IOREAD_BITS(_pdata, _reg, _field) \
GET_BITS(XI2C_IOREAD((_pdata), (_reg)), \
@@
-1610,7
+1635,8
@@
do { \
_reg##_##_field##_WIDTH)
#define XI2C_IOWRITE(_pdata, _reg, _val) \
_reg##_##_field##_WIDTH)
#define XI2C_IOWRITE(_pdata, _reg, _val) \
- rte_write32((_val), (void *)((_pdata)->xi2c_regs + (_reg)))
+ rte_write32((_val), \
+ (uint8_t *)((_pdata)->xi2c_regs) + (_reg))
#define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val) \
do { \
#define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val) \
do { \