+static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
+{
+ struct axgbe_port *pdata = dev->data->dev_private;
+ unsigned int val;
+
+ /* mtu setting is forbidden if port is start */
+ if (dev->data->dev_started) {
+ PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
+ dev->data->port_id);
+ return -EBUSY;
+ }
+ val = mtu > RTE_ETHER_MTU ? 1 : 0;
+ AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val);
+
+ return 0;
+}
+
+static void
+axgbe_update_tstamp_time(struct axgbe_port *pdata,
+ unsigned int sec, unsigned int nsec, int addsub)
+{
+ unsigned int count = 100;
+ uint32_t sub_val = 0;
+ uint32_t sub_val_sec = 0xFFFFFFFF;
+ uint32_t sub_val_nsec = 0x3B9ACA00;
+
+ if (addsub) {
+ if (sec)
+ sub_val = sub_val_sec - (sec - 1);
+ else
+ sub_val = sec;
+
+ AXGMAC_IOWRITE(pdata, MAC_STSUR, sub_val);
+ sub_val = sub_val_nsec - nsec;
+ AXGMAC_IOWRITE(pdata, MAC_STNUR, sub_val);
+ AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 1);
+ } else {
+ AXGMAC_IOWRITE(pdata, MAC_STSUR, sec);
+ AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 0);
+ AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
+ }
+ AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1);
+ /* Wait for time update to complete */
+ while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT))
+ rte_delay_ms(1);
+}
+
+static inline uint64_t
+div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder)
+{
+ *remainder = dividend % divisor;
+ return dividend / divisor;
+}
+
+static inline uint64_t
+div_u64(uint64_t dividend, uint32_t divisor)
+{
+ uint32_t remainder;
+ return div_u64_rem(dividend, divisor, &remainder);
+}
+
+static int
+axgbe_adjfreq(struct axgbe_port *pdata, int64_t delta)
+{
+ uint64_t adjust;
+ uint32_t addend, diff;
+ unsigned int neg_adjust = 0;
+
+ if (delta < 0) {
+ neg_adjust = 1;
+ delta = -delta;
+ }
+ adjust = (uint64_t)pdata->tstamp_addend;
+ adjust *= delta;
+ diff = (uint32_t)div_u64(adjust, 1000000000UL);
+ addend = (neg_adjust) ? pdata->tstamp_addend - diff :
+ pdata->tstamp_addend + diff;
+ pdata->tstamp_addend = addend;
+ axgbe_update_tstamp_addend(pdata, addend);
+ return 0;
+}
+
+static int
+axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
+{
+ struct axgbe_port *pdata = dev->data->dev_private;
+ struct timespec timestamp_delta;
+
+ axgbe_adjfreq(pdata, delta);
+ pdata->systime_tc.nsec += delta;
+
+ if (delta < 0) {
+ delta = -delta;
+ timestamp_delta = rte_ns_to_timespec(delta);
+ axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec,
+ timestamp_delta.tv_nsec, 1);
+ } else {
+ timestamp_delta = rte_ns_to_timespec(delta);
+ axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec,
+ timestamp_delta.tv_nsec, 0);
+ }
+ return 0;
+}
+
+static int
+axgbe_timesync_read_time(struct rte_eth_dev *dev,
+ struct timespec *timestamp)
+{
+ uint64_t nsec;
+ struct axgbe_port *pdata = dev->data->dev_private;
+
+ nsec = AXGMAC_IOREAD(pdata, MAC_STSR);
+ nsec *= NSEC_PER_SEC;
+ nsec += AXGMAC_IOREAD(pdata, MAC_STNR);
+ *timestamp = rte_ns_to_timespec(nsec);
+ return 0;
+}
+static int
+axgbe_timesync_write_time(struct rte_eth_dev *dev,
+ const struct timespec *timestamp)
+{
+ unsigned int count = 100;
+ struct axgbe_port *pdata = dev->data->dev_private;
+
+ AXGMAC_IOWRITE(pdata, MAC_STSUR, timestamp->tv_sec);
+ AXGMAC_IOWRITE(pdata, MAC_STNUR, timestamp->tv_nsec);
+ AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1);
+ /* Wait for time update to complete */
+ while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT))
+ rte_delay_ms(1);
+ if (!count)
+ PMD_DRV_LOG(ERR, "Timed out update timestamp\n");
+ return 0;
+}
+
+static void
+axgbe_update_tstamp_addend(struct axgbe_port *pdata,
+ uint32_t addend)
+{
+ unsigned int count = 100;
+
+ AXGMAC_IOWRITE(pdata, MAC_TSAR, addend);
+ AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1);
+
+ /* Wait for addend update to complete */
+ while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))
+ rte_delay_ms(1);
+ if (!count)
+ PMD_DRV_LOG(ERR, "Timed out updating timestamp addend register\n");
+}
+
+static void
+axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec,
+ unsigned int nsec)
+{
+ unsigned int count = 100;
+
+ /*System Time Sec Update*/
+ AXGMAC_IOWRITE(pdata, MAC_STSUR, sec);
+ /*System Time nanoSec Update*/
+ AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
+ /*Initialize Timestamp*/
+ AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1);
+
+ /* Wait for time update to complete */
+ while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))
+ rte_delay_ms(1);
+ if (!count)
+ PMD_DRV_LOG(ERR, "Timed out initializing timestamp\n");
+}
+
+static int
+axgbe_timesync_enable(struct rte_eth_dev *dev)
+{
+ struct axgbe_port *pdata = dev->data->dev_private;
+ unsigned int mac_tscr = 0;
+ uint64_t dividend;
+ struct timespec timestamp;
+ uint64_t nsec;
+
+ /* Set one nano-second accuracy */
+ AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1);
+
+ /* Set fine timestamp update */
+ AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1);
+
+ /* Overwrite earlier timestamps */
+ AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1);
+
+ AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
+
+ /* Enabling processing of ptp over eth pkt */
+ AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
+ AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
+ /* Enable timestamp for all pkts*/
+ AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
+
+ /* enabling timestamp */
+ AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
+ AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
+
+ /* Exit if timestamping is not enabled */
+ if (!AXGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) {
+ PMD_DRV_LOG(ERR, "Exiting as timestamp is not enabled\n");
+ return 0;
+ }
+
+ /* Sub-second Increment Value*/
+ AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, AXGBE_TSTAMP_SSINC);
+ /* Sub-nanosecond Increment Value */
+ AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, AXGBE_TSTAMP_SNSINC);
+
+ pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ;
+ dividend = 50000000;
+ dividend <<= 32;
+ pdata->tstamp_addend = div_u64(dividend, pdata->ptpclk_rate);
+
+ axgbe_update_tstamp_addend(pdata, pdata->tstamp_addend);
+ axgbe_set_tstamp_time(pdata, 0, 0);
+
+ /* Initialize the timecounter */
+ memset(&pdata->systime_tc, 0, sizeof(struct rte_timecounter));
+
+ pdata->systime_tc.cc_mask = AXGBE_CYCLECOUNTER_MASK;
+ pdata->systime_tc.cc_shift = 0;
+ pdata->systime_tc.nsec_mask = 0;
+
+ PMD_DRV_LOG(DEBUG, "Initializing system time counter with realtime\n");
+
+ /* Updating the counter once with clock real time */
+ clock_gettime(CLOCK_REALTIME, ×tamp);
+ nsec = rte_timespec_to_ns(×tamp);
+ nsec = rte_timecounter_update(&pdata->systime_tc, nsec);
+ axgbe_set_tstamp_time(pdata, timestamp.tv_sec, timestamp.tv_nsec);
+ return 0;
+}
+
+static int
+axgbe_timesync_disable(struct rte_eth_dev *dev)
+{
+ struct axgbe_port *pdata = dev->data->dev_private;
+ unsigned int mac_tscr = 0;
+
+ /*disable timestamp for all pkts*/
+ AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 0);
+ /*disable the addened register*/
+ AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 0);
+ /* disable timestamp update */
+ AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 0);
+ /*disable time stamp*/
+ AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 0);
+ return 0;
+}
+
+static int
+axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
+ struct timespec *timestamp, uint32_t flags)
+{
+ uint64_t nsec = 0;
+ volatile union axgbe_rx_desc *desc;
+ uint16_t idx, pmt;
+ struct axgbe_rx_queue *rxq = *dev->data->rx_queues;
+
+ idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
+ desc = &rxq->desc[idx];
+
+ while (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN))
+ rte_delay_ms(1);
+ if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CTXT)) {
+ if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_CONTEXT_DESC3, TSA) &&
+ !AXGMAC_GET_BITS_LE(desc->write.desc3,
+ RX_CONTEXT_DESC3, TSD)) {
+ pmt = AXGMAC_GET_BITS_LE(desc->write.desc3,
+ RX_CONTEXT_DESC3, PMT);
+ nsec = rte_le_to_cpu_32(desc->write.desc1);
+ nsec *= NSEC_PER_SEC;
+ nsec += rte_le_to_cpu_32(desc->write.desc0);
+ if (nsec != 0xffffffffffffffffULL) {
+ if (pmt == 0x01)
+ *timestamp = rte_ns_to_timespec(nsec);
+ PMD_DRV_LOG(DEBUG,
+ "flags = 0x%x nsec = %"PRIu64"\n",
+ flags, nsec);
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int
+axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
+ struct timespec *timestamp)
+{
+ uint64_t nsec;
+ struct axgbe_port *pdata = dev->data->dev_private;
+ unsigned int tx_snr, tx_ssr;
+
+ rte_delay_us(5);
+ if (pdata->vdata->tx_tstamp_workaround) {
+ tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR);
+ tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR);
+
+ } else {
+ tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR);
+ tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR);
+ }
+ if (AXGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) {
+ PMD_DRV_LOG(DEBUG, "Waiting for TXTSSTSMIS\n");
+ return 0;
+ }
+ nsec = tx_ssr;
+ nsec *= NSEC_PER_SEC;
+ nsec += tx_snr;
+ PMD_DRV_LOG(DEBUG, "nsec = %"PRIu64" tx_ssr = %d tx_snr = %d\n",
+ nsec, tx_ssr, tx_snr);
+ *timestamp = rte_ns_to_timespec(nsec);
+ return 0;
+}
+
+static int
+axgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on)
+{
+ struct axgbe_port *pdata = dev->data->dev_private;
+ unsigned long vid_bit, vid_idx;
+
+ vid_bit = VLAN_TABLE_BIT(vid);
+ vid_idx = VLAN_TABLE_IDX(vid);
+
+ if (on) {
+ PMD_DRV_LOG(DEBUG, "Set VLAN vid=%d for device = %s\n",
+ vid, pdata->eth_dev->device->name);
+ pdata->active_vlans[vid_idx] |= vid_bit;
+ } else {
+ PMD_DRV_LOG(DEBUG, "Reset VLAN vid=%d for device = %s\n",
+ vid, pdata->eth_dev->device->name);
+ pdata->active_vlans[vid_idx] &= ~vid_bit;
+ }
+ pdata->hw_if.update_vlan_hash_table(pdata);
+ return 0;
+}
+
+static int
+axgbe_vlan_tpid_set(struct rte_eth_dev *dev,
+ enum rte_vlan_type vlan_type,
+ uint16_t tpid)
+{
+ struct axgbe_port *pdata = dev->data->dev_private;
+ uint32_t reg = 0;
+ uint32_t qinq = 0;
+
+ qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP);
+ PMD_DRV_LOG(DEBUG, "EDVLP: qinq = 0x%x\n", qinq);
+
+ switch (vlan_type) {
+ case RTE_ETH_VLAN_TYPE_INNER:
+ PMD_DRV_LOG(DEBUG, "RTE_ETH_VLAN_TYPE_INNER\n");
+ if (qinq) {
+ if (tpid != 0x8100 && tpid != 0x88a8)
+ PMD_DRV_LOG(ERR,
+ "tag supported 0x8100/0x88A8\n");
+ PMD_DRV_LOG(DEBUG, "qinq with inner tag\n");
+
+ /*Enable Inner VLAN Tag */
+ AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERIVLT, 1);
+ reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, ERIVLT);
+ PMD_DRV_LOG(DEBUG, "bit ERIVLT = 0x%x\n", reg);
+
+ } else {
+ PMD_DRV_LOG(ERR,
+ "Inner type not supported in single tag\n");
+ }
+ break;
+ case RTE_ETH_VLAN_TYPE_OUTER:
+ PMD_DRV_LOG(DEBUG, "RTE_ETH_VLAN_TYPE_OUTER\n");
+ if (qinq) {
+ PMD_DRV_LOG(DEBUG, "double tagging is enabled\n");
+ /*Enable outer VLAN tag*/
+ AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERIVLT, 0);
+ reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, ERIVLT);
+ PMD_DRV_LOG(DEBUG, "bit ERIVLT = 0x%x\n", reg);
+
+ AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 1);
+ reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANIR, CSVL);
+ PMD_DRV_LOG(DEBUG, "bit CSVL = 0x%x\n", reg);
+ } else {
+ if (tpid != 0x8100 && tpid != 0x88a8)
+ PMD_DRV_LOG(ERR,
+ "tag supported 0x8100/0x88A8\n");
+ }
+ break;
+ case RTE_ETH_VLAN_TYPE_MAX:
+ PMD_DRV_LOG(ERR, "RTE_ETH_VLAN_TYPE_MAX\n");
+ break;
+ case RTE_ETH_VLAN_TYPE_UNKNOWN:
+ PMD_DRV_LOG(ERR, "RTE_ETH_VLAN_TYPE_UNKNOWN\n");
+ break;
+ }
+ return 0;
+}
+
+static void axgbe_vlan_extend_enable(struct axgbe_port *pdata)
+{
+ int qinq = 0;
+
+ AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EDVLP, 1);
+ qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP);
+ PMD_DRV_LOG(DEBUG, "vlan double tag enabled EDVLP:qinq=0x%x\n", qinq);
+}
+
+static void axgbe_vlan_extend_disable(struct axgbe_port *pdata)
+{
+ int qinq = 0;
+
+ AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EDVLP, 0);
+ qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP);
+ PMD_DRV_LOG(DEBUG, "vlan double tag disable EDVLP:qinq=0x%x\n", qinq);
+}
+
+static int
+axgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
+{
+ struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
+ struct axgbe_port *pdata = dev->data->dev_private;
+
+ /* Indicate that VLAN Tx CTAGs come from context descriptors */
+ AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0);
+ AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1);
+
+ if (mask & RTE_ETH_VLAN_STRIP_MASK) {
+ if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) {
+ PMD_DRV_LOG(DEBUG, "Strip ON for device = %s\n",
+ pdata->eth_dev->device->name);
+ pdata->hw_if.enable_rx_vlan_stripping(pdata);
+ } else {
+ PMD_DRV_LOG(DEBUG, "Strip OFF for device = %s\n",
+ pdata->eth_dev->device->name);
+ pdata->hw_if.disable_rx_vlan_stripping(pdata);
+ }
+ }
+ if (mask & RTE_ETH_VLAN_FILTER_MASK) {
+ if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
+ PMD_DRV_LOG(DEBUG, "Filter ON for device = %s\n",
+ pdata->eth_dev->device->name);
+ pdata->hw_if.enable_rx_vlan_filtering(pdata);
+ } else {
+ PMD_DRV_LOG(DEBUG, "Filter OFF for device = %s\n",
+ pdata->eth_dev->device->name);
+ pdata->hw_if.disable_rx_vlan_filtering(pdata);
+ }
+ }
+ if (mask & RTE_ETH_VLAN_EXTEND_MASK) {
+ if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) {
+ PMD_DRV_LOG(DEBUG, "enabling vlan extended mode\n");
+ axgbe_vlan_extend_enable(pdata);
+ /* Set global registers with default ethertype*/
+ axgbe_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_OUTER,
+ RTE_ETHER_TYPE_VLAN);
+ axgbe_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_INNER,
+ RTE_ETHER_TYPE_VLAN);
+ } else {
+ PMD_DRV_LOG(DEBUG, "disabling vlan extended mode\n");
+ axgbe_vlan_extend_disable(pdata);
+ }
+ }
+ return 0;
+}
+