+static void axgbe_an37_init(struct axgbe_port *pdata)
+{
+ unsigned int advertising;
+ unsigned int reg = 0;
+
+ advertising = pdata->phy_if.phy_impl.an_advertising(pdata);
+
+ reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
+ if (advertising & ADVERTISED_Pause)
+ reg |= 0x100;
+ else
+ reg &= ~0x100;
+ if (advertising & ADVERTISED_Asym_Pause)
+ reg |= 0x80;
+ else
+ reg &= ~0x80;
+
+ /* Full duplex, but not half */
+ reg |= AXGBE_AN_CL37_FD_MASK;
+ reg &= ~AXGBE_AN_CL37_HD_MASK;
+
+ XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg);
+
+ /* Set up the Control register */
+ reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
+ reg &= ~AXGBE_AN_CL37_TX_CONFIG_MASK;
+ reg &= ~AXGBE_AN_CL37_PCS_MODE_MASK;
+
+ switch (pdata->an_mode) {
+ case AXGBE_AN_MODE_CL37:
+ reg |= AXGBE_AN_CL37_PCS_MODE_BASEX;
+ break;
+ case AXGBE_AN_MODE_CL37_SGMII:
+ reg |= AXGBE_AN_CL37_PCS_MODE_SGMII;
+ break;
+ default:
+ break;
+ }
+ reg |= AXGBE_AN_CL37_MII_CTRL_8BIT;
+ XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
+}
+