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net/ixgbe/base: update X550 SFP identification
[dpdk.git]
/
drivers
/
net
/
bnx2x
/
bnx2x.h
diff --git
a/drivers/net/bnx2x/bnx2x.h
b/drivers/net/bnx2x/bnx2x.h
index
b3cd5fc
..
0f6024f
100644
(file)
--- a/
drivers/net/bnx2x/bnx2x.h
+++ b/
drivers/net/bnx2x/bnx2x.h
@@
-1,4
+1,4
@@
-/*
-
+/*
SPDX-License-Identifier: BSD-3-Clause
* Copyright (c) 2007-2013 Broadcom Corporation.
*
* Eric Davis <edavis@broadcom.com>
* Copyright (c) 2007-2013 Broadcom Corporation.
*
* Eric Davis <edavis@broadcom.com>
@@
-6,11
+6,9
@@
* Gary Zambrano <zambrano@broadcom.com>
*
* Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
* Gary Zambrano <zambrano@broadcom.com>
*
* Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
- * Copyright (c) 2015
QLogic Corporation
.
+ * Copyright (c) 2015
-2018 Cavium Inc
.
* All rights reserved.
* All rights reserved.
- * www.qlogic.com
- *
- * See LICENSE.bnx2x_pmd for copyright and licensing details.
+ * www.cavium.com
*/
#ifndef __BNX2X_H__
*/
#ifndef __BNX2X_H__
@@
-18,6
+16,7
@@
#include <rte_byteorder.h>
#include <rte_spinlock.h>
#include <rte_byteorder.h>
#include <rte_spinlock.h>
+#include <rte_bus_pci.h>
#include <rte_io.h>
#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
#include <rte_io.h>
#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
@@
-317,7
+316,7
@@
struct bnx2x_bar {
/* Used to manage DMA allocations. */
struct bnx2x_dma {
struct bnx2x_softc *sc;
/* Used to manage DMA allocations. */
struct bnx2x_dma {
struct bnx2x_softc *sc;
-
phys_addr_t
paddr;
+
rte_iova_t
paddr;
void *vaddr;
int nseg;
char msg[RTE_MEMZONE_NAMESIZE - 6];
void *vaddr;
int nseg;
char msg[RTE_MEMZONE_NAMESIZE - 6];
@@
-370,10
+369,10
@@
struct bnx2x_fastpath {
struct bnx2x_dma sb_dma;
union bnx2x_host_hc_status_block status_block;
struct bnx2x_dma sb_dma;
union bnx2x_host_hc_status_block status_block;
-
phys_addr
_t tx_desc_mapping;
+
rte_iova
_t tx_desc_mapping;
-
phys_addr
_t rx_desc_mapping;
-
phys_addr
_t rx_comp_mapping;
+
rte_iova
_t rx_desc_mapping;
+
rte_iova
_t rx_comp_mapping;
uint16_t *sb_index_values;
uint16_t *sb_running_index;
uint16_t *sb_index_values;
uint16_t *sb_running_index;
@@
-468,7
+467,7
@@
union cdu_context {
struct hw_context {
struct bnx2x_dma vcxt_dma;
union cdu_context *vcxt;
struct hw_context {
struct bnx2x_dma vcxt_dma;
union cdu_context *vcxt;
- //
phys_addr
_t cxt_mapping;
+ //
rte_iova
_t cxt_mapping;
size_t size;
};
size_t size;
};
@@
-1242,7
+1241,7
@@
struct bnx2x_softc {
uint32_t gz_outlen;
#define GUNZIP_BUF(sc) (sc->gz_buf)
#define GUNZIP_OUTLEN(sc) (sc->gz_outlen)
uint32_t gz_outlen;
#define GUNZIP_BUF(sc) (sc->gz_buf)
#define GUNZIP_OUTLEN(sc) (sc->gz_outlen)
-#define GUNZIP_PHYS(sc) (
phys_addr
_t)(sc->gz_buf_dma.paddr)
+#define GUNZIP_PHYS(sc) (
rte_iova
_t)(sc->gz_buf_dma.paddr)
#define FW_BUF_SIZE 0x40000
struct raw_op *init_ops;
#define FW_BUF_SIZE 0x40000
struct raw_op *init_ops;
@@
-1310,14
+1309,14
@@
struct bnx2x_softc {
*/
int fw_stats_req_size;
struct bnx2x_fw_stats_req *fw_stats_req;
*/
int fw_stats_req_size;
struct bnx2x_fw_stats_req *fw_stats_req;
-
phys_addr
_t fw_stats_req_mapping;
+
rte_iova
_t fw_stats_req_mapping;
/*
* FW statistics data shortcut (points at the beginning of fw_stats
* buffer + fw_stats_req_size).
*/
int fw_stats_data_size;
struct bnx2x_fw_stats_data *fw_stats_data;
/*
* FW statistics data shortcut (points at the beginning of fw_stats
* buffer + fw_stats_req_size).
*/
int fw_stats_data_size;
struct bnx2x_fw_stats_data *fw_stats_data;
-
phys_addr
_t fw_stats_data_mapping;
+
rte_iova
_t fw_stats_data_mapping;
/* tracking a pending STAT_QUERY ramrod */
uint16_t stats_pending;
/* tracking a pending STAT_QUERY ramrod */
uint16_t stats_pending;
@@
-1402,8
+1401,8
@@
union bnx2x_stats_show_data {
#define FUNC_FLG_LEADING 0x0020 /* PF only */
struct bnx2x_func_init_params {
#define FUNC_FLG_LEADING 0x0020 /* PF only */
struct bnx2x_func_init_params {
-
phys_addr
_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */
-
phys_addr
_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */
+
rte_iova
_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */
+
rte_iova
_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */
uint16_t func_flgs;
uint16_t func_id; /* abs function id */
uint16_t pf_id;
uint16_t func_flgs;
uint16_t func_id; /* abs function id */
uint16_t pf_id;
@@
-1525,12
+1524,12
@@
bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset)
#define REG_RD_DMAE(sc, offset, valp, len32) \
do { \
(void)bnx2x_read_dmae(sc, offset, len32); \
#define REG_RD_DMAE(sc, offset, valp, len32) \
do { \
(void)bnx2x_read_dmae(sc, offset, len32); \
-
(void)
rte_memcpy(valp, BNX2X_SP(sc, wb_data[0]), (len32) * 4); \
+ rte_memcpy(valp, BNX2X_SP(sc, wb_data[0]), (len32) * 4); \
} while (0)
#define REG_WR_DMAE(sc, offset, valp, len32) \
do { \
} while (0)
#define REG_WR_DMAE(sc, offset, valp, len32) \
do { \
-
(void)
rte_memcpy(BNX2X_SP(sc, wb_data[0]), valp, (len32) * 4); \
+ rte_memcpy(BNX2X_SP(sc, wb_data[0]), valp, (len32) * 4); \
(void)bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data), offset, len32); \
} while (0)
(void)bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data), offset, len32); \
} while (0)
@@
-1748,7
+1747,7
@@
uint32_t bnx2x_dmae_opcode(struct bnx2x_softc *sc, uint8_t src_type,
uint8_t comp_type);
void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx);
void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32);
uint8_t comp_type);
void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx);
void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32);
-void bnx2x_write_dmae(struct bnx2x_softc *sc,
phys_addr
_t dma_addr,
+void bnx2x_write_dmae(struct bnx2x_softc *sc,
rte_iova
_t dma_addr,
uint32_t dst_addr, uint32_t len32);
void bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
uint32_t cid);
uint32_t dst_addr, uint32_t len32);
void bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
uint32_t cid);
@@
-1929,6
+1928,7
@@
void bnx2x_link_status_update(struct bnx2x_softc *sc);
int bnx2x_complete_sp(struct bnx2x_softc *sc);
int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc);
void bnx2x_periodic_callout(struct bnx2x_softc *sc);
int bnx2x_complete_sp(struct bnx2x_softc *sc);
int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc);
void bnx2x_periodic_callout(struct bnx2x_softc *sc);
+void bnx2x_periodic_stop(void *param);
int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_count);
void bnx2x_vf_close(struct bnx2x_softc *sc);
int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_count);
void bnx2x_vf_close(struct bnx2x_softc *sc);
@@
-1977,7
+1977,7
@@
bnx2x_set_rx_mode(struct bnx2x_softc *sc)
static inline int pci_read(struct bnx2x_softc *sc, size_t addr,
void *val, uint8_t size)
{
static inline int pci_read(struct bnx2x_softc *sc, size_t addr,
void *val, uint8_t size)
{
- if (rte_
eal_
pci_read_config(sc->pci_dev, val, size, addr) <= 0) {
+ if (rte_pci_read_config(sc->pci_dev, val, size, addr) <= 0) {
PMD_DRV_LOG(ERR, "Can't read from PCI config space");
return ENXIO;
}
PMD_DRV_LOG(ERR, "Can't read from PCI config space");
return ENXIO;
}
@@
-1989,7
+1989,7
@@
static inline int pci_write_word(struct bnx2x_softc *sc, size_t addr, off_t val)
{
uint16_t val16 = val;
{
uint16_t val16 = val;
- if (rte_
eal_
pci_write_config(sc->pci_dev, &val16,
+ if (rte_pci_write_config(sc->pci_dev, &val16,
sizeof(val16), addr) <= 0) {
PMD_DRV_LOG(ERR, "Can't write to PCI config space");
return ENXIO;
sizeof(val16), addr) <= 0) {
PMD_DRV_LOG(ERR, "Can't write to PCI config space");
return ENXIO;
@@
-2001,7
+2001,7
@@
static inline int pci_write_word(struct bnx2x_softc *sc, size_t addr, off_t val)
static inline int pci_write_long(struct bnx2x_softc *sc, size_t addr, off_t val)
{
uint32_t val32 = val;
static inline int pci_write_long(struct bnx2x_softc *sc, size_t addr, off_t val)
{
uint32_t val32 = val;
- if (rte_
eal_
pci_write_config(sc->pci_dev, &val32,
+ if (rte_pci_write_config(sc->pci_dev, &val32,
sizeof(val32), addr) <= 0) {
PMD_DRV_LOG(ERR, "Can't write to PCI config space");
return ENXIO;
sizeof(val32), addr) <= 0) {
PMD_DRV_LOG(ERR, "Can't write to PCI config space");
return ENXIO;