+struct bnxt_error_recovery_info {
+ /* All units in milliseconds */
+ uint32_t driver_polling_freq;
+ uint32_t master_func_wait_period;
+ uint32_t normal_func_wait_period;
+ uint32_t master_func_wait_period_after_reset;
+ uint32_t max_bailout_time_after_reset;
+#define BNXT_FW_STATUS_REG 0
+#define BNXT_FW_HEARTBEAT_CNT_REG 1
+#define BNXT_FW_RECOVERY_CNT_REG 2
+#define BNXT_FW_RESET_INPROG_REG 3
+#define BNXT_FW_STATUS_REG_CNT 4
+ uint32_t status_regs[BNXT_FW_STATUS_REG_CNT];
+ uint32_t mapped_status_regs[BNXT_FW_STATUS_REG_CNT];
+ uint32_t reset_inprogress_reg_mask;
+#define BNXT_NUM_RESET_REG 16
+ uint8_t reg_array_cnt;
+ uint32_t reset_reg[BNXT_NUM_RESET_REG];
+ uint32_t reset_reg_val[BNXT_NUM_RESET_REG];
+ uint8_t delay_after_reset[BNXT_NUM_RESET_REG];
+#define BNXT_FLAG_ERROR_RECOVERY_HOST BIT(0)
+#define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1)
+#define BNXT_FLAG_MASTER_FUNC BIT(2)
+#define BNXT_FLAG_RECOVERY_ENABLED BIT(3)
+ uint32_t flags;
+
+ uint32_t last_heart_beat;
+ uint32_t last_reset_counter;
+};
+
+/* address space location of register */
+#define BNXT_FW_STATUS_REG_TYPE_MASK 3
+/* register is located in PCIe config space */
+#define BNXT_FW_STATUS_REG_TYPE_CFG 0
+/* register is located in GRC address space */
+#define BNXT_FW_STATUS_REG_TYPE_GRC 1
+/* register is located in BAR0 */
+#define BNXT_FW_STATUS_REG_TYPE_BAR0 2
+/* register is located in BAR1 */
+#define BNXT_FW_STATUS_REG_TYPE_BAR1 3
+
+#define BNXT_FW_STATUS_REG_TYPE(reg) ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK)
+#define BNXT_FW_STATUS_REG_OFF(reg) ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK)
+
+#define BNXT_GRCP_WINDOW_2_BASE 0x2000
+#define BNXT_GRCP_WINDOW_3_BASE 0x3000
+
+#define BNXT_FW_STATUS_SHUTDOWN 0x100000
+