+/* Convert Bit field location to value */
+#define ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
+ (1 << HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE)
+#define ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
+ (1 << HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED)
+#define ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
+ (1 << HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE)
+#define ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
+ (1 << HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE)
+#define ASYNC_CMPL_EVENT_ID_RESET_NOTIFY \
+ (1 << HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY)
+#define ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY \
+ (1 << HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY)
+#define ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
+ (1 << (HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD - 32))
+#define ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE \
+ (1 << (HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE - 32))
+#define ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION \
+ (1 << (HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION - 32))
+#define ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
+ (1 << (HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE - 32))
+
+#define HWRM_QUEUE_SERVICE_PROFILE_LOSSY \
+ HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY
+
+#define HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN \
+ HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
+
+#define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC \
+ HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
+#define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL \
+ HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL
+
+#define HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED \
+ HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAM4_LINK_SPEED
+#define HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK \
+ HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAM4_LINK_SPEED_MASK
+#define HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK \
+ HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK
+
+#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED \
+ HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED
+
+#define HWRM_SPEC_CODE_1_8_4 0x10804
+#define HWRM_SPEC_CODE_1_9_0 0x10900
+#define HWRM_SPEC_CODE_1_9_2 0x10902
+
+#define FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES \
+ (HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP | \
+ HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ | \
+ HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ | \
+ HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC | \
+ HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT)
+
+#define GET_TX_QUEUE_INFO(x) \
+ bp->tx_cos_queue[x].id = resp->queue_id##x; \
+ bp->tx_cos_queue[x].profile = \
+ resp->queue_id##x##_service_profile
+
+#define GET_RX_QUEUE_INFO(x) \
+ bp->rx_cos_queue[x].id = resp->queue_id##x; \
+ bp->rx_cos_queue[x].profile = \
+ resp->queue_id##x##_service_profile
+
+int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
+ bool use_kong_mb,
+ uint16_t tf_type,
+ uint16_t tf_subtype,
+ uint32_t *tf_response_code,
+ void *msg,
+ uint32_t msg_len,
+ void *response,
+ uint32_t response_len);
+
+int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
+ bool use_kong_mb,
+ uint16_t msg_type,
+ void *msg,
+ uint32_t msg_len,
+ void *resp_msg,
+ uint32_t resp_len);
+
+#define CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC \
+ HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC
+
+enum bnxt_flow_dir {
+ BNXT_DIR_RX = 0,
+ BNXT_DIR_TX,
+ BNXT_DIR_LOOPBACK,
+ BNXT_DIR_MAX
+};
+
+struct bnxt_pf_resource_info {
+ uint16_t num_rsscos_ctxs;
+ uint16_t num_stat_ctxs;
+ uint16_t num_tx_rings;
+ uint16_t num_rx_rings;
+ uint16_t num_cp_rings;
+ uint16_t num_l2_ctxs;
+ uint32_t num_hw_ring_grps;
+};
+
+#define BNXT_CTX_VAL_INVAL 0xFFFF