+
+ if (nq_ring_info) {
+ struct bnxt_ring *nq_ring = nq_ring_info->cp_ring_struct;
+
+ nq_ring->bd = (char *)mz->addr + nq_ring_start;
+ nq_ring->bd_dma = mz_phys_addr + nq_ring_start;
+ nq_ring_info->cp_desc_ring = nq_ring->bd;
+ nq_ring_info->cp_desc_mapping = nq_ring->bd_dma;
+ nq_ring->mem_zone = (const void *)mz;
+
+ if (!nq_ring->bd)
+ return -ENOMEM;
+ if (nq_ring->vmem_size)
+ *nq_ring->vmem = (char *)mz->addr + nq_vmem_start;
+
+ nq_ring_info->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
+ }
+
+ return 0;
+}
+
+static void bnxt_init_dflt_coal(struct bnxt_coal *coal)
+{
+ /* Tick values in micro seconds.
+ * 1 coal_buf x bufs_per_record = 1 completion record.
+ */
+ coal->num_cmpl_aggr_int = BNXT_NUM_CMPL_AGGR_INT;
+ /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
+ coal->num_cmpl_dma_aggr = BNXT_NUM_CMPL_DMA_AGGR;
+ /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
+ coal->num_cmpl_dma_aggr_during_int = BNXT_NUM_CMPL_DMA_AGGR_DURING_INT;
+ coal->int_lat_tmr_max = BNXT_INT_LAT_TMR_MAX;
+ /* min timer set to 1/2 of interrupt timer */
+ coal->int_lat_tmr_min = BNXT_INT_LAT_TMR_MIN;
+ /* buf timer set to 1/4 of interrupt timer */
+ coal->cmpl_aggr_dma_tmr = BNXT_CMPL_AGGR_DMA_TMR;
+ coal->cmpl_aggr_dma_tmr_during_int = BNXT_CMPL_AGGR_DMA_TMR_DURING_INT;
+}
+
+static void bnxt_set_db(struct bnxt *bp,
+ struct bnxt_db_info *db,
+ uint32_t ring_type,
+ uint32_t map_idx,
+ uint32_t fid)
+{
+ if (BNXT_CHIP_THOR(bp)) {
+ if (BNXT_PF(bp))
+ db->doorbell = (char *)bp->doorbell_base + 0x10000;
+ else
+ db->doorbell = (char *)bp->doorbell_base + 0x4000;
+ switch (ring_type) {
+ case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
+ db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
+ break;
+ case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
+ case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
+ db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
+ break;
+ case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
+ db->db_key64 = DBR_PATH_L2 | DBR_TYPE_CQ;
+ break;
+ case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
+ db->db_key64 = DBR_PATH_L2;
+ break;
+ }
+ db->db_key64 |= (uint64_t)fid << DBR_XID_SFT;
+ db->db_64 = true;
+ } else {
+ db->doorbell = (char *)bp->doorbell_base + map_idx * 0x80;
+ switch (ring_type) {
+ case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
+ db->db_key32 = DB_KEY_TX;
+ break;
+ case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
+ db->db_key32 = DB_KEY_RX;
+ break;
+ case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
+ db->db_key32 = DB_KEY_CP;
+ break;
+ }
+ db->db_64 = false;
+ }
+}
+
+static int bnxt_alloc_cmpl_ring(struct bnxt *bp, int queue_index,
+ struct bnxt_cp_ring_info *cpr)
+{
+ struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
+ uint32_t nq_ring_id = HWRM_NA_SIGNATURE;
+ int cp_ring_index = queue_index + BNXT_RX_VEC_START;
+ struct bnxt_cp_ring_info *nqr = bp->rxtx_nq_ring;
+ uint8_t ring_type;
+ int rc = 0;
+
+ ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL;
+
+ if (BNXT_HAS_NQ(bp)) {
+ if (nqr) {
+ nq_ring_id = nqr->cp_ring_struct->fw_ring_id;
+ } else {
+ PMD_DRV_LOG(ERR, "NQ ring is NULL\n");
+ return -EINVAL;
+ }
+ }
+
+ rc = bnxt_hwrm_ring_alloc(bp, cp_ring, ring_type, cp_ring_index,
+ HWRM_NA_SIGNATURE, nq_ring_id, 0);
+ if (rc)
+ return rc;
+
+ cpr->cp_cons = 0;
+ bnxt_set_db(bp, &cpr->cp_db, ring_type, cp_ring_index,
+ cp_ring->fw_ring_id);
+ bnxt_db_cq(cpr);
+
+ return 0;
+}
+
+int bnxt_alloc_rxtx_nq_ring(struct bnxt *bp)
+{
+ struct bnxt_cp_ring_info *nqr;
+ struct bnxt_ring *ring;
+ int ring_index = BNXT_NUM_ASYNC_CPR(bp);
+ unsigned int socket_id;
+ uint8_t ring_type;
+ int rc = 0;
+
+ if (!BNXT_HAS_NQ(bp) || bp->rxtx_nq_ring)
+ return 0;
+
+ socket_id = rte_lcore_to_socket_id(rte_get_master_lcore());
+
+ nqr = rte_zmalloc_socket("nqr",
+ sizeof(struct bnxt_cp_ring_info),
+ RTE_CACHE_LINE_SIZE, socket_id);
+ if (nqr == NULL)
+ return -ENOMEM;
+
+ ring = rte_zmalloc_socket("bnxt_cp_ring_struct",
+ sizeof(struct bnxt_ring),
+ RTE_CACHE_LINE_SIZE, socket_id);
+ if (ring == NULL) {
+ rte_free(nqr);
+ return -ENOMEM;
+ }
+
+ ring->bd = (void *)nqr->cp_desc_ring;
+ ring->bd_dma = nqr->cp_desc_mapping;
+ ring->ring_size = rte_align32pow2(DEFAULT_CP_RING_SIZE);
+ ring->ring_mask = ring->ring_size - 1;
+ ring->vmem_size = 0;
+ ring->vmem = NULL;
+
+ nqr->cp_ring_struct = ring;
+ rc = bnxt_alloc_rings(bp, 0, NULL, NULL, nqr, NULL, "l2_nqr");
+ if (rc) {
+ rte_free(ring);
+ rte_free(nqr);
+ return -ENOMEM;
+ }
+
+ ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ;
+
+ rc = bnxt_hwrm_ring_alloc(bp, ring, ring_type, ring_index,
+ HWRM_NA_SIGNATURE, HWRM_NA_SIGNATURE, 0);
+ if (rc) {
+ rte_free(ring);
+ rte_free(nqr);
+ return rc;
+ }
+
+ bnxt_set_db(bp, &nqr->cp_db, ring_type, ring_index,
+ ring->fw_ring_id);
+ bnxt_db_nq(nqr);
+
+ bp->rxtx_nq_ring = nqr;
+
+ return 0;
+}
+
+/* Free RX/TX NQ ring. */
+void bnxt_free_rxtx_nq_ring(struct bnxt *bp)
+{
+ struct bnxt_cp_ring_info *nqr = bp->rxtx_nq_ring;
+
+ if (!nqr)
+ return;
+
+ bnxt_free_nq_ring(bp, nqr);
+
+ bnxt_free_ring(nqr->cp_ring_struct);
+ rte_free(nqr->cp_ring_struct);
+ nqr->cp_ring_struct = NULL;
+ rte_free(nqr);
+ bp->rxtx_nq_ring = NULL;
+}
+
+static int bnxt_alloc_rx_ring(struct bnxt *bp, int queue_index)
+{
+ struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
+ struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
+ struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
+ struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
+ struct bnxt_ring *ring = rxr->rx_ring_struct;
+ uint8_t ring_type;
+ int rc = 0;
+
+ ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_RX;
+
+ rc = bnxt_hwrm_ring_alloc(bp, ring, ring_type,
+ queue_index, cpr->hw_stats_ctx_id,
+ cp_ring->fw_ring_id, 0);
+ if (rc)
+ return rc;
+
+ rxr->rx_prod = 0;
+ if (BNXT_HAS_RING_GRPS(bp))
+ bp->grp_info[queue_index].rx_fw_ring_id = ring->fw_ring_id;
+ bnxt_set_db(bp, &rxr->rx_db, ring_type, queue_index, ring->fw_ring_id);
+ bnxt_db_write(&rxr->rx_db, rxr->rx_prod);
+
+ return 0;
+}
+
+static int bnxt_alloc_rx_agg_ring(struct bnxt *bp, int queue_index)
+{
+ unsigned int map_idx = queue_index + bp->rx_cp_nr_rings;
+ struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
+ struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
+ struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
+ struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
+ struct bnxt_ring *ring = rxr->ag_ring_struct;
+ uint32_t hw_stats_ctx_id = HWRM_NA_SIGNATURE;
+ uint8_t ring_type;
+ int rc = 0;
+
+ ring->fw_rx_ring_id = rxr->rx_ring_struct->fw_ring_id;
+
+ if (BNXT_CHIP_THOR(bp)) {
+ ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG;
+ hw_stats_ctx_id = cpr->hw_stats_ctx_id;
+ } else {
+ ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_RX;
+ }
+
+ rc = bnxt_hwrm_ring_alloc(bp, ring, ring_type, map_idx,
+ hw_stats_ctx_id, cp_ring->fw_ring_id, 0);
+
+ if (rc)
+ return rc;
+
+ rxr->ag_prod = 0;
+ if (BNXT_HAS_RING_GRPS(bp))
+ bp->grp_info[queue_index].ag_fw_ring_id = ring->fw_ring_id;
+ bnxt_set_db(bp, &rxr->ag_db, ring_type, map_idx, ring->fw_ring_id);
+ bnxt_db_write(&rxr->ag_db, rxr->ag_prod);
+
+ return 0;
+}
+
+int bnxt_alloc_hwrm_rx_ring(struct bnxt *bp, int queue_index)
+{
+ struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
+ struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
+ struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
+ struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
+ int rc;
+
+ rc = bnxt_alloc_cmpl_ring(bp, queue_index, cpr);
+ if (rc)
+ goto err_out;
+
+ if (BNXT_HAS_RING_GRPS(bp)) {
+ bp->grp_info[queue_index].fw_stats_ctx = cpr->hw_stats_ctx_id;
+ bp->grp_info[queue_index].cp_fw_ring_id = cp_ring->fw_ring_id;
+ }
+
+ if (!BNXT_NUM_ASYNC_CPR(bp) && !queue_index) {
+ /*
+ * If a dedicated async event completion ring is not enabled,
+ * use the first completion ring from PF or VF as the default
+ * completion ring for async event handling.
+ */
+ bp->async_cp_ring = cpr;
+ rc = bnxt_hwrm_set_async_event_cr(bp);
+ if (rc)
+ goto err_out;
+ }
+
+ rc = bnxt_alloc_rx_ring(bp, queue_index);
+ if (rc)
+ goto err_out;
+
+ rc = bnxt_alloc_rx_agg_ring(bp, queue_index);
+ if (rc)
+ goto err_out;
+
+ if (rxq->rx_started) {
+ if (bnxt_init_one_rx_ring(rxq)) {
+ PMD_DRV_LOG(ERR,
+ "bnxt_init_one_rx_ring failed!\n");
+ bnxt_rx_queue_release_op(rxq);
+ rc = -ENOMEM;
+ goto err_out;
+ }
+ bnxt_db_write(&rxr->rx_db, rxr->rx_prod);
+ bnxt_db_write(&rxr->ag_db, rxr->ag_prod);
+ }
+ rxq->index = queue_index;
+#ifdef RTE_ARCH_X86
+ bnxt_rxq_vec_setup(rxq);
+#endif
+