+static int bnxt_rx_pages(struct bnxt_rx_queue *rxq,
+ struct rte_mbuf *mbuf, uint32_t *tmp_raw_cons,
+ uint8_t agg_buf, struct bnxt_tpa_info *tpa_info)
+{
+ struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
+ struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
+ int i;
+ uint16_t cp_cons, ag_cons;
+ struct rx_pkt_cmpl *rxcmp;
+ struct rte_mbuf *last = mbuf;
+ bool is_p5_tpa = tpa_info && BNXT_CHIP_P5(rxq->bp);
+
+ for (i = 0; i < agg_buf; i++) {
+ struct rte_mbuf **ag_buf;
+ struct rte_mbuf *ag_mbuf;
+
+ if (is_p5_tpa) {
+ rxcmp = (void *)&tpa_info->agg_arr[i];
+ } else {
+ *tmp_raw_cons = NEXT_RAW_CMP(*tmp_raw_cons);
+ cp_cons = RING_CMP(cpr->cp_ring_struct, *tmp_raw_cons);
+ rxcmp = (struct rx_pkt_cmpl *)
+ &cpr->cp_desc_ring[cp_cons];
+ }
+
+#ifdef BNXT_DEBUG
+ bnxt_dump_cmpl(cp_cons, rxcmp);
+#endif
+
+ ag_cons = rxcmp->opaque;
+ RTE_ASSERT(ag_cons <= rxr->ag_ring_struct->ring_mask);
+ ag_buf = &rxr->ag_buf_ring[ag_cons];
+ ag_mbuf = *ag_buf;
+ RTE_ASSERT(ag_mbuf != NULL);
+
+ ag_mbuf->data_len = rte_le_to_cpu_16(rxcmp->len);
+
+ mbuf->nb_segs++;
+ mbuf->pkt_len += ag_mbuf->data_len;
+
+ last->next = ag_mbuf;
+ last = ag_mbuf;
+
+ *ag_buf = NULL;
+
+ /*
+ * As aggregation buffer consumed out of order in TPA module,
+ * use bitmap to track freed slots to be allocated and notified
+ * to NIC
+ */
+ rte_bitmap_set(rxr->ag_bitmap, ag_cons);
+ }
+ last->next = NULL;
+ bnxt_prod_ag_mbuf(rxq);
+ return 0;
+}
+
+static inline struct rte_mbuf *bnxt_tpa_end(
+ struct bnxt_rx_queue *rxq,
+ uint32_t *raw_cp_cons,
+ struct rx_tpa_end_cmpl *tpa_end,
+ struct rx_tpa_end_cmpl_hi *tpa_end1)
+{
+ struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
+ struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
+ uint16_t agg_id;
+ struct rte_mbuf *mbuf;
+ uint8_t agg_bufs;
+ uint8_t payload_offset;
+ struct bnxt_tpa_info *tpa_info;
+
+ if (BNXT_CHIP_P5(rxq->bp)) {
+ struct rx_tpa_v2_end_cmpl *th_tpa_end;
+ struct rx_tpa_v2_end_cmpl_hi *th_tpa_end1;
+
+ th_tpa_end = (void *)tpa_end;
+ th_tpa_end1 = (void *)tpa_end1;
+ agg_id = BNXT_TPA_END_AGG_ID_TH(th_tpa_end);
+ agg_bufs = BNXT_TPA_END_AGG_BUFS_TH(th_tpa_end1);
+ payload_offset = th_tpa_end1->payload_offset;
+ } else {
+ agg_id = BNXT_TPA_END_AGG_ID(tpa_end);
+ agg_bufs = BNXT_TPA_END_AGG_BUFS(tpa_end);
+ if (!bnxt_agg_bufs_valid(cpr, agg_bufs, *raw_cp_cons))
+ return NULL;
+ payload_offset = tpa_end->payload_offset;
+ }
+
+ tpa_info = &rxr->tpa_info[agg_id];
+ mbuf = tpa_info->mbuf;
+ RTE_ASSERT(mbuf != NULL);
+
+ if (agg_bufs) {
+ bnxt_rx_pages(rxq, mbuf, raw_cp_cons, agg_bufs, tpa_info);
+ }
+ mbuf->l4_len = payload_offset;
+
+ struct rte_mbuf *new_data = __bnxt_alloc_rx_data(rxq->mb_pool);
+ RTE_ASSERT(new_data != NULL);
+ if (!new_data) {
+ rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail);
+ return NULL;
+ }
+ tpa_info->mbuf = new_data;
+
+ return mbuf;
+}
+
+uint32_t bnxt_ptype_table[BNXT_PTYPE_TBL_DIM] __rte_cache_aligned;
+
+static void __rte_cold
+bnxt_init_ptype_table(void)
+{
+ uint32_t *pt = bnxt_ptype_table;
+ static bool initialized;
+ int ip6, tun, type;
+ uint32_t l3;
+ int i;
+
+ if (initialized)
+ return;
+
+ for (i = 0; i < BNXT_PTYPE_TBL_DIM; i++) {
+ if (i & (RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN >> 2))
+ pt[i] = RTE_PTYPE_L2_ETHER_VLAN;
+ else
+ pt[i] = RTE_PTYPE_L2_ETHER;
+
+ ip6 = i & (RX_PKT_CMPL_FLAGS2_IP_TYPE >> 7);
+ tun = i & (RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC >> 2);
+ type = (i & 0x78) << 9;
+
+ if (!tun && !ip6)
+ l3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
+ else if (!tun && ip6)
+ l3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
+ else if (tun && !ip6)
+ l3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
+ else
+ l3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
+
+ switch (type) {
+ case RX_PKT_CMPL_FLAGS_ITYPE_ICMP:
+ if (tun)
+ pt[i] |= l3 | RTE_PTYPE_INNER_L4_ICMP;
+ else
+ pt[i] |= l3 | RTE_PTYPE_L4_ICMP;
+ break;
+ case RX_PKT_CMPL_FLAGS_ITYPE_TCP:
+ if (tun)
+ pt[i] |= l3 | RTE_PTYPE_INNER_L4_TCP;
+ else
+ pt[i] |= l3 | RTE_PTYPE_L4_TCP;
+ break;
+ case RX_PKT_CMPL_FLAGS_ITYPE_UDP:
+ if (tun)
+ pt[i] |= l3 | RTE_PTYPE_INNER_L4_UDP;
+ else
+ pt[i] |= l3 | RTE_PTYPE_L4_UDP;
+ break;
+ case RX_PKT_CMPL_FLAGS_ITYPE_IP:
+ pt[i] |= l3;
+ break;
+ }
+ }
+ initialized = true;
+}
+
+static uint32_t
+bnxt_parse_pkt_type(struct rx_pkt_cmpl *rxcmp, struct rx_pkt_cmpl_hi *rxcmp1)
+{
+ uint32_t flags_type, flags2;
+ uint8_t index;
+
+ flags_type = rte_le_to_cpu_16(rxcmp->flags_type);
+ flags2 = rte_le_to_cpu_32(rxcmp1->flags2);
+
+ /*
+ * Index format:
+ * bit 0: RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC
+ * bit 1: RX_CMPL_FLAGS2_IP_TYPE
+ * bit 2: RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN
+ * bits 3-6: RX_PKT_CMPL_FLAGS_ITYPE
+ */
+ index = ((flags_type & RX_PKT_CMPL_FLAGS_ITYPE_MASK) >> 9) |
+ ((flags2 & (RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN |
+ RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC)) >> 2) |
+ ((flags2 & RX_PKT_CMPL_FLAGS2_IP_TYPE) >> 7);
+
+ return bnxt_ptype_table[index];
+}
+
+static void __rte_cold
+bnxt_init_ol_flags_tables(struct bnxt_rx_queue *rxq)
+{
+ struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
+ struct rte_eth_conf *dev_conf;
+ bool outer_cksum_enabled;
+ uint64_t offloads;
+ uint32_t *pt;
+ int i;
+
+ dev_conf = &rxq->bp->eth_dev->data->dev_conf;
+ offloads = dev_conf->rxmode.offloads;
+
+ outer_cksum_enabled = !!(offloads & (DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
+ DEV_RX_OFFLOAD_OUTER_UDP_CKSUM));
+
+ /* Initialize ol_flags table. */
+ pt = rxr->ol_flags_table;
+ for (i = 0; i < BNXT_OL_FLAGS_TBL_DIM; i++) {
+ pt[i] = 0;
+
+ if (i & RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN)
+ pt[i] |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
+
+ if (i & (RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC << 3)) {
+ /* Tunnel case. */
+ if (outer_cksum_enabled) {
+ if (i & RX_PKT_CMPL_FLAGS2_IP_CS_CALC)
+ pt[i] |= PKT_RX_IP_CKSUM_GOOD;
+
+ if (i & RX_PKT_CMPL_FLAGS2_L4_CS_CALC)
+ pt[i] |= PKT_RX_L4_CKSUM_GOOD;
+
+ if (i & RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC)
+ pt[i] |= PKT_RX_OUTER_L4_CKSUM_GOOD;
+ } else {
+ if (i & RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC)
+ pt[i] |= PKT_RX_IP_CKSUM_GOOD;
+
+ if (i & RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC)
+ pt[i] |= PKT_RX_L4_CKSUM_GOOD;
+ }
+ } else {
+ /* Non-tunnel case. */
+ if (i & RX_PKT_CMPL_FLAGS2_IP_CS_CALC)
+ pt[i] |= PKT_RX_IP_CKSUM_GOOD;
+
+ if (i & RX_PKT_CMPL_FLAGS2_L4_CS_CALC)
+ pt[i] |= PKT_RX_L4_CKSUM_GOOD;
+ }
+ }
+
+ /* Initialize checksum error table. */
+ pt = rxr->ol_flags_err_table;
+ for (i = 0; i < BNXT_OL_FLAGS_ERR_TBL_DIM; i++) {
+ pt[i] = 0;
+
+ if (i & (RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC << 2)) {
+ /* Tunnel case. */
+ if (outer_cksum_enabled) {
+ if (i & (RX_PKT_CMPL_ERRORS_IP_CS_ERROR >> 4))
+ pt[i] |= PKT_RX_IP_CKSUM_BAD;
+
+ if (i & (RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR >> 4))
+ pt[i] |= PKT_RX_EIP_CKSUM_BAD;
+
+ if (i & (RX_PKT_CMPL_ERRORS_L4_CS_ERROR >> 4))
+ pt[i] |= PKT_RX_L4_CKSUM_BAD;
+
+ if (i & (RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR >> 4))
+ pt[i] |= PKT_RX_OUTER_L4_CKSUM_BAD;
+ } else {
+ if (i & (RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR >> 4))
+ pt[i] |= PKT_RX_IP_CKSUM_BAD;
+
+ if (i & (RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR >> 4))
+ pt[i] |= PKT_RX_L4_CKSUM_BAD;
+ }
+ } else {
+ /* Non-tunnel case. */
+ if (i & (RX_PKT_CMPL_ERRORS_IP_CS_ERROR >> 4))
+ pt[i] |= PKT_RX_IP_CKSUM_BAD;
+
+ if (i & (RX_PKT_CMPL_ERRORS_L4_CS_ERROR >> 4))
+ pt[i] |= PKT_RX_L4_CKSUM_BAD;
+ }
+ }
+}
+
+static void
+bnxt_set_ol_flags(struct bnxt_rx_ring_info *rxr, struct rx_pkt_cmpl *rxcmp,
+ struct rx_pkt_cmpl_hi *rxcmp1, struct rte_mbuf *mbuf)
+{
+ uint16_t flags_type, errors, flags;
+ uint64_t ol_flags;
+
+ flags_type = rte_le_to_cpu_16(rxcmp->flags_type);
+
+ flags = rte_le_to_cpu_32(rxcmp1->flags2) &
+ (RX_PKT_CMPL_FLAGS2_IP_CS_CALC |
+ RX_PKT_CMPL_FLAGS2_L4_CS_CALC |
+ RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC |
+ RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC |
+ RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN);
+
+ flags |= (flags & RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC) << 3;
+ errors = rte_le_to_cpu_16(rxcmp1->errors_v2) &
+ (RX_PKT_CMPL_ERRORS_IP_CS_ERROR |
+ RX_PKT_CMPL_ERRORS_L4_CS_ERROR |
+ RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR |
+ RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR);
+ errors = (errors >> 4) & flags;
+
+ ol_flags = rxr->ol_flags_table[flags & ~errors];
+
+ if (unlikely(errors)) {
+ errors |= (flags & RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC) << 2;
+ ol_flags |= rxr->ol_flags_err_table[errors];
+ }
+
+ if (flags_type & RX_PKT_CMPL_FLAGS_RSS_VALID) {
+ mbuf->hash.rss = rte_le_to_cpu_32(rxcmp->rss_hash);
+ ol_flags |= PKT_RX_RSS_HASH;
+ }
+
+#ifdef RTE_LIBRTE_IEEE1588
+ if (unlikely((flags_type & RX_PKT_CMPL_FLAGS_MASK) ==
+ RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP))
+ ol_flags |= PKT_RX_IEEE1588_PTP | PKT_RX_IEEE1588_TMST;
+#endif
+
+ mbuf->ol_flags = ol_flags;
+}
+
+#ifdef RTE_LIBRTE_IEEE1588
+static void
+bnxt_get_rx_ts_p5(struct bnxt *bp, uint32_t rx_ts_cmpl)
+{
+ uint64_t systime_cycles = 0;
+
+ if (!BNXT_CHIP_P5(bp))
+ return;
+
+ /* On Thor, Rx timestamps are provided directly in the
+ * Rx completion records to the driver. Only 32 bits of
+ * the timestamp is present in the completion. Driver needs
+ * to read the current 48 bit free running timer using the
+ * HWRM_PORT_TS_QUERY command and combine the upper 16 bits
+ * from the HWRM response with the lower 32 bits in the
+ * Rx completion to produce the 48 bit timestamp for the Rx packet
+ */
+ bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
+ &systime_cycles);
+ bp->ptp_cfg->rx_timestamp = (systime_cycles & 0xFFFF00000000);
+ bp->ptp_cfg->rx_timestamp |= rx_ts_cmpl;
+}
+#endif
+
+static uint32_t
+bnxt_ulp_set_mark_in_mbuf(struct bnxt *bp, struct rx_pkt_cmpl_hi *rxcmp1,
+ struct rte_mbuf *mbuf, uint32_t *vfr_flag)
+{
+ uint32_t cfa_code;
+ uint32_t meta_fmt;
+ uint32_t meta;
+ bool gfid = false;
+ uint32_t mark_id;
+ uint32_t flags2;
+ uint32_t gfid_support = 0;
+ int rc;
+
+ if (BNXT_GFID_ENABLED(bp))
+ gfid_support = 1;
+
+ cfa_code = rte_le_to_cpu_16(rxcmp1->cfa_code);
+ flags2 = rte_le_to_cpu_32(rxcmp1->flags2);
+ meta = rte_le_to_cpu_32(rxcmp1->metadata);
+
+ /*
+ * The flags field holds extra bits of info from [6:4]
+ * which indicate if the flow is in TCAM or EM or EEM
+ */
+ meta_fmt = (flags2 & BNXT_CFA_META_FMT_MASK) >>
+ BNXT_CFA_META_FMT_SHFT;
+
+ switch (meta_fmt) {
+ case 0:
+ if (gfid_support) {
+ /* Not an LFID or GFID, a flush cmd. */
+ goto skip_mark;
+ } else {
+ /* LFID mode, no vlan scenario */
+ gfid = false;
+ }
+ break;
+ case 4:
+ case 5:
+ /*
+ * EM/TCAM case
+ * Assume that EM doesn't support Mark due to GFID
+ * collisions with EEM. Simply return without setting the mark
+ * in the mbuf.
+ */
+ if (BNXT_CFA_META_EM_TEST(meta)) {
+ /*This is EM hit {EM(1), GFID[27:16], 19'd0 or vtag } */
+ gfid = true;
+ meta >>= BNXT_RX_META_CFA_CODE_SHIFT;
+ cfa_code |= meta << BNXT_CFA_CODE_META_SHIFT;
+ } else {
+ /*
+ * It is a TCAM entry, so it is an LFID.
+ * The TCAM IDX and Mode can also be determined
+ * by decoding the meta_data. We are not
+ * using these for now.
+ */
+ }
+ break;
+ case 6:
+ case 7:
+ /* EEM Case, only using gfid in EEM for now. */
+ gfid = true;
+
+ /*
+ * For EEM flows, The first part of cfa_code is 16 bits.
+ * The second part is embedded in the
+ * metadata field from bit 19 onwards. The driver needs to
+ * ignore the first 19 bits of metadata and use the next 12
+ * bits as higher 12 bits of cfa_code.
+ */
+ meta >>= BNXT_RX_META_CFA_CODE_SHIFT;
+ cfa_code |= meta << BNXT_CFA_CODE_META_SHIFT;
+ break;
+ default:
+ /* For other values, the cfa_code is assumed to be an LFID. */
+ break;
+ }
+
+ rc = ulp_mark_db_mark_get(bp->ulp_ctx, gfid,
+ cfa_code, vfr_flag, &mark_id);
+ if (!rc) {
+ /* VF to VFR Rx path. So, skip mark_id injection in mbuf */
+ if (vfr_flag && *vfr_flag)
+ return mark_id;
+ /* Got the mark, write it to the mbuf and return */
+ mbuf->hash.fdir.hi = mark_id;
+ *bnxt_cfa_code_dynfield(mbuf) = cfa_code & 0xffffffffull;
+ mbuf->hash.fdir.id = rxcmp1->cfa_code;
+ mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
+ return mark_id;
+ }
+
+skip_mark:
+ mbuf->hash.fdir.hi = 0;
+ mbuf->hash.fdir.id = 0;
+
+ return 0;
+}
+
+void bnxt_set_mark_in_mbuf(struct bnxt *bp,
+ struct rx_pkt_cmpl_hi *rxcmp1,
+ struct rte_mbuf *mbuf)
+{
+ uint32_t cfa_code = 0;
+ uint8_t meta_fmt = 0;
+ uint16_t flags2 = 0;
+ uint32_t meta = 0;
+
+ cfa_code = rte_le_to_cpu_16(rxcmp1->cfa_code);
+ if (!cfa_code)
+ return;
+
+ if (cfa_code && !bp->mark_table[cfa_code].valid)
+ return;
+
+ flags2 = rte_le_to_cpu_16(rxcmp1->flags2);
+ meta = rte_le_to_cpu_32(rxcmp1->metadata);
+ if (meta) {
+ meta >>= BNXT_RX_META_CFA_CODE_SHIFT;
+
+ /* The flags field holds extra bits of info from [6:4]
+ * which indicate if the flow is in TCAM or EM or EEM
+ */
+ meta_fmt = (flags2 & BNXT_CFA_META_FMT_MASK) >>
+ BNXT_CFA_META_FMT_SHFT;
+
+ /* meta_fmt == 4 => 'b100 => 'b10x => EM.
+ * meta_fmt == 5 => 'b101 => 'b10x => EM + VLAN
+ * meta_fmt == 6 => 'b110 => 'b11x => EEM
+ * meta_fmt == 7 => 'b111 => 'b11x => EEM + VLAN.
+ */
+ meta_fmt >>= BNXT_CFA_META_FMT_EM_EEM_SHFT;
+ }
+
+ mbuf->hash.fdir.hi = bp->mark_table[cfa_code].mark_id;
+ mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
+}
+
+static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
+ struct bnxt_rx_queue *rxq, uint32_t *raw_cons)