+ (*(uint32_t *)db = (DB_KEY_RX | (prod)))
+
+#define BNXT_TPA_L4_SIZE(x) \
+ { \
+ typeof(x) hdr_info = (x); \
+ (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32) \
+ }
+
+#define BNXT_TPA_INNER_L3_OFF(hdr_info) \
+ (((hdr_info) >> 18) & 0x1ff)
+
+#define BNXT_TPA_INNER_L2_OFF(hdr_info) \
+ (((hdr_info) >> 9) & 0x1ff)
+
+#define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
+ ((hdr_info) & 0x1ff)
+
+#define flags2_0xf(rxcmp1) \
+ (((rxcmp1)->flags2) & 0xf)
+
+/* IP non tunnel can be with or without L4-
+ * Ether / (vlan) / IP|IP6 / UDP|TCP|SCTP Or
+ * Ether / (vlan) / outer IP|IP6 / ICMP
+ * we use '==' instead of '&' because tunnel pkts have all 4 fields set.
+ */
+#define IS_IP_NONTUNNEL_PKT(flags2_f) \
+ ( \
+ ((flags2_f) == \
+ (rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_CS_CALC))) || \
+ ((flags2_f) == \
+ (rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_CS_CALC | \
+ RX_PKT_CMPL_FLAGS2_L4_CS_CALC))) \
+ )
+
+/* IP Tunnel pkt must have atleast tunnel-IP-calc set.
+ * again tunnel ie outer L4 is optional bcoz of
+ * Ether / (vlan) / outer IP|IP6 / GRE / Ether / IP|IP6 / UDP|TCP|SCTP
+ * Ether / (vlan) / outer IP|IP6 / outer UDP / VxLAN / Ether / IP|IP6 /
+ * UDP|TCP|SCTP
+ * Ether / (vlan) / outer IP|IP6 / outer UDP / VXLAN-GPE / Ether / IP|IP6 /
+ * UDP|TCP|SCTP
+ * Ether / (vlan) / outer IP|IP6 / outer UDP / VXLAN-GPE / IP|IP6 /
+ * UDP|TCP|SCTP
+ * Ether / (vlan) / outer IP|IP6 / GRE / IP|IP6 / UDP|TCP|SCTP
+ * Ether / (vlan) / outer IP|IP6 / IP|IP6 / UDP|TCP|SCTP
+ * also inner L3 chksum error is not taken into consideration by DPDK.
+ */
+#define IS_IP_TUNNEL_PKT(flags2_f) \
+ ((flags2_f) & rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC))
+
+/* RX_PKT_CMPL_ERRORS_IP_CS_ERROR only for Non-tunnel pkts.
+ * For tunnel pkts RX_PKT_CMPL_ERRORS_IP_CS_ERROR is not accounted and treated
+ * as good csum pkt.
+ */
+#define RX_CMP_IP_CS_ERROR(rxcmp1) \
+ ((rxcmp1)->errors_v2 & \
+ rte_cpu_to_le_32(RX_PKT_CMPL_ERRORS_IP_CS_ERROR))
+
+#define RX_CMP_IP_OUTER_CS_ERROR(rxcmp1) \
+ ((rxcmp1)->errors_v2 & \
+ rte_cpu_to_le_32(RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR))
+
+#define RX_CMP_IP_CS_BITS \
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_CS_CALC | \
+ RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC)
+
+#define RX_CMP_IP_CS_UNKNOWN(rxcmp1) \
+ !((rxcmp1)->flags2 & RX_CMP_IP_CS_BITS)
+
+/* L4 non tunnel pkt-
+ * Ether / (vlan) / IP6 / UDP|TCP|SCTP
+ */
+#define IS_L4_NONTUNNEL_PKT(flags2_f) \
+ ( \
+ ((flags2_f) == \
+ (rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_CS_CALC | \
+ RX_PKT_CMPL_FLAGS2_L4_CS_CALC))))
+
+/* L4 tunnel pkt-
+ * Outer L4 is not mandatory. Eg: GRE-
+ * Ether / (vlan) / outer IP|IP6 / GRE / Ether / IP|IP6 / UDP|TCP|SCTP
+ * Ether / (vlan) / outer IP|IP6 / outer UDP / VxLAN / Ether / IP|IP6 /
+ * UDP|TCP|SCTP
+ */
+#define IS_L4_TUNNEL_PKT_INNER_OUTER_L4_CS(flags2_f) \
+ ((flags2_f) == \
+ (rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_CS_CALC | \
+ RX_PKT_CMPL_FLAGS2_L4_CS_CALC | \
+ RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC | \
+ RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC)))
+
+#define IS_L4_TUNNEL_PKT_ONLY_INNER_L4_CS(flags2_f) \
+ ((flags2_f) == \
+ (rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_CS_CALC | \
+ RX_PKT_CMPL_FLAGS2_L4_CS_CALC | \
+ RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC)))
+
+#define IS_L4_TUNNEL_PKT(flags2_f) \
+ ( \
+ IS_L4_TUNNEL_PKT_INNER_OUTER_L4_CS(flags2_f) || \
+ IS_L4_TUNNEL_PKT_ONLY_INNER_L4_CS(flags2_f) \
+ )
+
+#define BNXT_TPA_START_AGG_ID_PRE_TH(cmp) \
+ ((rte_le_to_cpu_16((cmp)->agg_id) & RX_TPA_START_CMPL_AGG_ID_MASK) >> \
+ RX_TPA_START_CMPL_AGG_ID_SFT)
+
+#define BNXT_TPA_START_AGG_ID_TH(cmp) \
+ rte_le_to_cpu_16((cmp)->agg_id)
+
+static inline uint16_t bnxt_tpa_start_agg_id(struct bnxt *bp,
+ struct rx_tpa_start_cmpl *cmp)
+{
+ if (BNXT_CHIP_THOR(bp))
+ return BNXT_TPA_START_AGG_ID_TH(cmp);
+ else
+ return BNXT_TPA_START_AGG_ID_PRE_TH(cmp);
+}
+
+#define BNXT_TPA_END_AGG_BUFS(cmp) \
+ (((cmp)->agg_bufs_v1 & RX_TPA_END_CMPL_AGG_BUFS_MASK) \
+ >> RX_TPA_END_CMPL_AGG_BUFS_SFT)
+
+#define BNXT_TPA_END_AGG_BUFS_TH(cmp) \
+ ((cmp)->tpa_agg_bufs)
+
+#define BNXT_TPA_END_AGG_ID(cmp) \
+ (((cmp)->agg_id & RX_TPA_END_CMPL_AGG_ID_MASK) >> \
+ RX_TPA_END_CMPL_AGG_ID_SFT)
+
+#define BNXT_TPA_END_AGG_ID_TH(cmp) \
+ rte_le_to_cpu_16((cmp)->agg_id)
+
+#define RX_CMP_L4_CS_BITS \
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_L4_CS_CALC)
+
+#define RX_CMP_L4_CS_UNKNOWN(rxcmp1) \
+ !((rxcmp1)->flags2 & RX_CMP_L4_CS_BITS)
+
+#define RX_CMP_T_L4_CS_BITS \
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC)
+
+#define RX_CMP_T_L4_CS_UNKNOWN(rxcmp1) \
+ !((rxcmp1)->flags2 & RX_CMP_T_L4_CS_BITS)
+
+/* Outer L4 chksum error
+ */
+#define RX_CMP_L4_OUTER_CS_ERR2(rxcmp1) \
+ ((rxcmp1)->errors_v2 & \
+ rte_cpu_to_le_32(RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR))
+
+/* Inner L4 chksum error
+ */
+#define RX_CMP_L4_INNER_CS_ERR2(rxcmp1) \
+ ((rxcmp1)->errors_v2 & \
+ rte_cpu_to_le_32(RX_PKT_CMPL_ERRORS_L4_CS_ERROR))
+
+#define BNXT_RX_POST_THRESH 32
+
+enum pkt_hash_types {
+ PKT_HASH_TYPE_NONE, /* Undefined type */
+ PKT_HASH_TYPE_L2, /* Input: src_MAC, dest_MAC */
+ PKT_HASH_TYPE_L3, /* Input: src_IP, dst_IP */
+ PKT_HASH_TYPE_L4, /* Input: src_IP, dst_IP, src_port, dst_port */
+};
+
+struct bnxt_tpa_info {
+ struct rte_mbuf *mbuf;
+ uint16_t len;
+ uint32_t agg_count;
+ struct rx_tpa_v2_abuf_cmpl agg_arr[TPA_MAX_NUM_SEGS];
+};