+
+int
+cnxk_nix_dev_get_reg(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)
+{
+ struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+ struct roc_nix *nix = &dev->nix;
+ uint64_t *data = regs->data;
+ int rc = -ENOTSUP;
+
+ if (data == NULL) {
+ rc = roc_nix_lf_get_reg_count(nix);
+ if (rc > 0) {
+ regs->length = rc;
+ regs->width = 8;
+ rc = 0;
+ }
+ return rc;
+ }
+
+ if (!regs->length ||
+ regs->length == (uint32_t)roc_nix_lf_get_reg_count(nix))
+ return roc_nix_lf_reg_dump(nix, data);
+
+ return rc;
+}
+
+int
+cnxk_nix_reta_update(struct rte_eth_dev *eth_dev,
+ struct rte_eth_rss_reta_entry64 *reta_conf,
+ uint16_t reta_size)
+{
+ struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+ uint16_t reta[ROC_NIX_RSS_RETA_MAX];
+ struct roc_nix *nix = &dev->nix;
+ int i, j, rc = -EINVAL, idx = 0;
+
+ if (reta_size != dev->nix.reta_sz) {
+ plt_err("Size of hash lookup table configured (%d) does not "
+ "match the number hardware can supported (%d)",
+ reta_size, dev->nix.reta_sz);
+ goto fail;
+ }
+
+ roc_nix_rss_reta_get(nix, 0, reta);
+
+ /* Copy RETA table */
+ for (i = 0; i < (int)(dev->nix.reta_sz / RTE_ETH_RETA_GROUP_SIZE); i++) {
+ for (j = 0; j < RTE_ETH_RETA_GROUP_SIZE; j++) {
+ if ((reta_conf[i].mask >> j) & 0x01)
+ reta[idx] = reta_conf[i].reta[j];
+ idx++;
+ }
+ }
+
+ return roc_nix_rss_reta_set(nix, 0, reta);
+
+fail:
+ return rc;
+}
+
+int
+cnxk_nix_reta_query(struct rte_eth_dev *eth_dev,
+ struct rte_eth_rss_reta_entry64 *reta_conf,
+ uint16_t reta_size)
+{
+ struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+ uint16_t reta[ROC_NIX_RSS_RETA_MAX];
+ struct roc_nix *nix = &dev->nix;
+ int rc = -EINVAL, i, j, idx = 0;
+
+ if (reta_size != dev->nix.reta_sz) {
+ plt_err("Size of hash lookup table configured (%d) does not "
+ "match the number hardware can supported (%d)",
+ reta_size, dev->nix.reta_sz);
+ goto fail;
+ }
+
+ rc = roc_nix_rss_reta_get(nix, 0, reta);
+ if (rc)
+ goto fail;
+
+ /* Copy RETA table */
+ for (i = 0; i < (int)(dev->nix.reta_sz / RTE_ETH_RETA_GROUP_SIZE); i++) {
+ for (j = 0; j < RTE_ETH_RETA_GROUP_SIZE; j++) {
+ if ((reta_conf[i].mask >> j) & 0x01)
+ reta_conf[i].reta[j] = reta[idx];
+ idx++;
+ }
+ }
+
+ return 0;
+
+fail:
+ return rc;
+}
+
+int
+cnxk_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
+ struct rte_eth_rss_conf *rss_conf)
+{
+ struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+ struct roc_nix *nix = &dev->nix;
+ uint8_t rss_hash_level;
+ uint32_t flowkey_cfg;
+ int rc = -EINVAL;
+ uint8_t alg_idx;
+
+ if (rss_conf->rss_key && rss_conf->rss_key_len != ROC_NIX_RSS_KEY_LEN) {
+ plt_err("Hash key size mismatch %d vs %d",
+ rss_conf->rss_key_len, ROC_NIX_RSS_KEY_LEN);
+ goto fail;
+ }
+
+ if (rss_conf->rss_key)
+ roc_nix_rss_key_set(nix, rss_conf->rss_key);
+
+ rss_hash_level = RTE_ETH_RSS_LEVEL(rss_conf->rss_hf);
+ if (rss_hash_level)
+ rss_hash_level -= 1;
+ flowkey_cfg =
+ cnxk_rss_ethdev_to_nix(dev, rss_conf->rss_hf, rss_hash_level);
+
+ rc = roc_nix_rss_flowkey_set(nix, &alg_idx, flowkey_cfg,
+ ROC_NIX_RSS_GROUP_DEFAULT,
+ ROC_NIX_RSS_MCAM_IDX_DEFAULT);
+ if (rc) {
+ plt_err("Failed to set RSS hash function rc=%d", rc);
+ return rc;
+ }
+
+fail:
+ return rc;
+}
+
+int
+cnxk_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
+ struct rte_eth_rss_conf *rss_conf)
+{
+ struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+
+ if (rss_conf->rss_key)
+ roc_nix_rss_key_get(&dev->nix, rss_conf->rss_key);
+
+ rss_conf->rss_key_len = ROC_NIX_RSS_KEY_LEN;
+ rss_conf->rss_hf = dev->ethdev_rss_hf;
+
+ return 0;
+}
+
+int
+cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev,
+ struct rte_ether_addr *mc_addr_set,
+ uint32_t nb_mc_addr)
+{
+ struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+ struct rte_eth_dev_data *data = eth_dev->data;
+ struct rte_ether_addr null_mac_addr;
+ struct roc_nix *nix = &dev->nix;
+ int rc, index;
+ uint32_t i;
+
+ memset(&null_mac_addr, 0, sizeof(null_mac_addr));
+
+ /* All configured multicast filters should be flushed first */
+ for (i = 0; i < dev->max_mac_entries; i++) {
+ if (rte_is_multicast_ether_addr(&data->mac_addrs[i])) {
+ rc = roc_nix_mac_addr_del(nix, i);
+ if (rc) {
+ plt_err("Failed to flush mcast address, rc=%d",
+ rc);
+ return rc;
+ }
+
+ dev->dmac_filter_count--;
+ /* Update address in NIC data structure */
+ rte_ether_addr_copy(&null_mac_addr,
+ &data->mac_addrs[i]);
+ }
+ }
+
+ if (!mc_addr_set || !nb_mc_addr)
+ return 0;
+
+ /* Check for available space */
+ if (nb_mc_addr >
+ ((uint32_t)(dev->max_mac_entries - dev->dmac_filter_count))) {
+ plt_err("No space is available to add multicast filters");
+ return -ENOSPC;
+ }
+
+ /* Multicast addresses are to be installed */
+ for (i = 0; i < nb_mc_addr; i++) {
+ index = roc_nix_mac_addr_add(nix, mc_addr_set[i].addr_bytes);
+ if (index < 0) {
+ plt_err("Failed to add mcast mac address, rc=%d",
+ index);
+ return index;
+ }
+
+ dev->dmac_filter_count++;
+ /* Update address in NIC data structure */
+ rte_ether_addr_copy(&mc_addr_set[i], &data->mac_addrs[index]);
+ }
+
+ roc_nix_npc_promisc_ena_dis(nix, true);
+ dev->dmac_filter_enable = true;
+ eth_dev->data->promiscuous = false;
+
+ return 0;
+}
+
+int
+nix_priority_flow_ctrl_configure(struct rte_eth_dev *eth_dev,
+ struct cnxk_pfc_cfg *conf)
+{
+ enum roc_nix_fc_mode mode_map[] = {ROC_NIX_FC_NONE, ROC_NIX_FC_RX,
+ ROC_NIX_FC_TX, ROC_NIX_FC_FULL};
+ struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+ struct rte_eth_dev_data *data = eth_dev->data;
+ struct cnxk_pfc_cfg *pfc = &dev->pfc_cfg;
+ struct roc_nix *nix = &dev->nix;
+ struct roc_nix_pfc_cfg pfc_cfg;
+ struct roc_nix_fc_cfg fc_cfg;
+ struct cnxk_eth_rxq_sp *rxq;
+ struct cnxk_eth_txq_sp *txq;
+ uint8_t rx_pause, tx_pause;
+ enum rte_eth_fc_mode mode;
+ struct roc_nix_cq *cq;
+ struct roc_nix_sq *sq;
+ int rc;
+
+ if (roc_nix_is_vf_or_sdp(nix)) {
+ plt_err("Prio flow ctrl config is not allowed on VF and SDP");
+ return -ENOTSUP;
+ }
+
+ if (roc_model_is_cn96_ax() && data->dev_started) {
+ /* On Ax, CQ should be in disabled state
+ * while setting flow control configuration.
+ */
+ plt_info("Stop the port=%d for setting flow control",
+ data->port_id);
+ return 0;
+ }
+
+ if (dev->pfc_tc_sq_map[conf->tx_tc] != 0xFFFF &&
+ dev->pfc_tc_sq_map[conf->tx_tc] != conf->tx_qid) {
+ plt_err("Same TC can not be configured on multiple SQs");
+ return -ENOTSUP;
+ }
+
+ mode = conf->fc_cfg.mode;
+ rx_pause = (mode == RTE_ETH_FC_FULL) || (mode == RTE_ETH_FC_RX_PAUSE);
+ tx_pause = (mode == RTE_ETH_FC_FULL) || (mode == RTE_ETH_FC_TX_PAUSE);
+
+ /* Configure CQs */
+ memset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg));
+ rxq = ((struct cnxk_eth_rxq_sp *)data->rx_queues[conf->rx_qid]) - 1;
+ cq = &dev->cqs[rxq->qid];
+ fc_cfg.type = ROC_NIX_FC_CQ_CFG;
+ fc_cfg.cq_cfg.tc = conf->rx_tc;
+ fc_cfg.cq_cfg.enable = !!tx_pause;
+ fc_cfg.cq_cfg.rq = cq->qid;
+ fc_cfg.cq_cfg.cq_drop = cq->drop_thresh;
+ rc = roc_nix_fc_config_set(nix, &fc_cfg);
+ if (rc)
+ goto exit;
+
+ /* Check if RX pause frame is enabled or not */
+ if (pfc->fc_cfg.rx_pause ^ rx_pause) {
+ if (conf->tx_qid >= eth_dev->data->nb_tx_queues)
+ goto exit;
+
+ if ((roc_nix_tm_tree_type_get(nix) == ROC_NIX_TM_DEFAULT) &&
+ eth_dev->data->nb_tx_queues > 1) {
+ /*
+ * Disabled xmit will be enabled when
+ * new topology is available.
+ */
+ rc = roc_nix_tm_hierarchy_disable(nix);
+ if (rc)
+ goto exit;
+
+ rc = roc_nix_tm_pfc_prepare_tree(nix);
+ if (rc)
+ goto exit;
+
+ rc = roc_nix_tm_hierarchy_enable(nix, ROC_NIX_TM_PFC,
+ true);
+ if (rc)
+ goto exit;
+ }
+ }
+
+ txq = ((struct cnxk_eth_txq_sp *)data->tx_queues[conf->tx_qid]) - 1;
+ sq = &dev->sqs[txq->qid];
+ memset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg));
+ fc_cfg.type = ROC_NIX_FC_TM_CFG;
+ fc_cfg.tm_cfg.sq = sq->qid;
+ fc_cfg.tm_cfg.tc = conf->tx_tc;
+ fc_cfg.tm_cfg.enable = !!rx_pause;
+ rc = roc_nix_fc_config_set(nix, &fc_cfg);
+ if (rc)
+ return rc;
+
+ dev->pfc_tc_sq_map[conf->tx_tc] = sq->qid;
+
+ /* Configure MAC block */
+ if (tx_pause)
+ pfc->class_en |= BIT(conf->rx_tc);
+ else
+ pfc->class_en &= ~BIT(conf->rx_tc);
+
+ if (pfc->class_en)
+ mode = RTE_ETH_FC_FULL;
+
+ memset(&pfc_cfg, 0, sizeof(struct roc_nix_pfc_cfg));
+ pfc_cfg.mode = mode_map[mode];
+ pfc_cfg.tc = pfc->class_en;
+ rc = roc_nix_pfc_mode_set(nix, &pfc_cfg);
+ if (rc)
+ return rc;
+
+ pfc->fc_cfg.rx_pause = rx_pause;
+ pfc->fc_cfg.tx_pause = tx_pause;
+ pfc->fc_cfg.mode = mode;
+
+exit:
+ return rc;
+}