+uint16_t
+dpaa_free_mbuf(const struct qm_fd *fd)
+{
+ struct rte_mbuf *mbuf;
+ struct dpaa_bp_info *bp_info;
+ uint8_t format;
+ void *ptr;
+
+ bp_info = DPAA_BPID_TO_POOL_INFO(fd->bpid);
+ format = (fd->opaque & DPAA_FD_FORMAT_MASK) >> DPAA_FD_FORMAT_SHIFT;
+ if (unlikely(format == qm_fd_sg)) {
+ struct rte_mbuf *first_seg, *prev_seg, *cur_seg, *temp;
+ struct qm_sg_entry *sgt, *sg_temp;
+ void *vaddr, *sg_vaddr;
+ int i = 0;
+ uint16_t fd_offset = fd->offset;
+
+ vaddr = DPAA_MEMPOOL_PTOV(bp_info, qm_fd_addr(fd));
+ if (!vaddr) {
+ DPAA_PMD_ERR("unable to convert physical address");
+ return -1;
+ }
+ sgt = vaddr + fd_offset;
+ sg_temp = &sgt[i++];
+ hw_sg_to_cpu(sg_temp);
+ temp = (struct rte_mbuf *)
+ ((char *)vaddr - bp_info->meta_data_size);
+ sg_vaddr = DPAA_MEMPOOL_PTOV(bp_info,
+ qm_sg_entry_get64(sg_temp));
+
+ first_seg = (struct rte_mbuf *)((char *)sg_vaddr -
+ bp_info->meta_data_size);
+ first_seg->nb_segs = 1;
+ prev_seg = first_seg;
+ while (i < DPAA_SGT_MAX_ENTRIES) {
+ sg_temp = &sgt[i++];
+ hw_sg_to_cpu(sg_temp);
+ sg_vaddr = DPAA_MEMPOOL_PTOV(bp_info,
+ qm_sg_entry_get64(sg_temp));
+ cur_seg = (struct rte_mbuf *)((char *)sg_vaddr -
+ bp_info->meta_data_size);
+ first_seg->nb_segs += 1;
+ prev_seg->next = cur_seg;
+ if (sg_temp->final) {
+ cur_seg->next = NULL;
+ break;
+ }
+ prev_seg = cur_seg;
+ }
+
+ rte_pktmbuf_free_seg(temp);
+ rte_pktmbuf_free_seg(first_seg);
+ return 0;
+ }
+
+ ptr = DPAA_MEMPOOL_PTOV(bp_info, qm_fd_addr(fd));
+ mbuf = (struct rte_mbuf *)((char *)ptr - bp_info->meta_data_size);
+
+ rte_pktmbuf_free(mbuf);
+
+ return 0;
+}
+
+/* Specific for LS1043 */
+void
+dpaa_rx_cb_no_prefetch(struct qman_fq **fq, struct qm_dqrr_entry **dqrr,
+ void **bufs, int num_bufs)
+{
+ struct rte_mbuf *mbuf;
+ struct dpaa_bp_info *bp_info;
+ const struct qm_fd *fd;
+ void *ptr;
+ struct dpaa_if *dpaa_intf;
+ uint16_t offset, i;
+ uint32_t length;
+ uint8_t format;
+
+ bp_info = DPAA_BPID_TO_POOL_INFO(dqrr[0]->fd.bpid);
+ ptr = rte_dpaa_mem_ptov(qm_fd_addr(&dqrr[0]->fd));
+ rte_prefetch0((void *)((uint8_t *)ptr + DEFAULT_RX_ICEOF));
+ bufs[0] = (struct rte_mbuf *)((char *)ptr - bp_info->meta_data_size);
+
+ for (i = 0; i < num_bufs; i++) {
+ if (i < num_bufs - 1) {
+ bp_info = DPAA_BPID_TO_POOL_INFO(dqrr[i + 1]->fd.bpid);
+ ptr = rte_dpaa_mem_ptov(qm_fd_addr(&dqrr[i + 1]->fd));
+ rte_prefetch0((void *)((uint8_t *)ptr +
+ DEFAULT_RX_ICEOF));
+ bufs[i + 1] = (struct rte_mbuf *)((char *)ptr -
+ bp_info->meta_data_size);
+ }
+
+ fd = &dqrr[i]->fd;
+ dpaa_intf = fq[0]->dpaa_intf;
+ format = (fd->opaque & DPAA_FD_FORMAT_MASK) >>
+ DPAA_FD_FORMAT_SHIFT;
+ if (unlikely(format == qm_fd_sg)) {
+ bufs[i] = dpaa_eth_sg_to_mbuf(fd, dpaa_intf->ifid);
+ continue;
+ }
+
+ offset = (fd->opaque & DPAA_FD_OFFSET_MASK) >>
+ DPAA_FD_OFFSET_SHIFT;
+ length = fd->opaque & DPAA_FD_LENGTH_MASK;
+
+ mbuf = bufs[i];
+ mbuf->data_off = offset;
+ mbuf->data_len = length;
+ mbuf->pkt_len = length;
+ mbuf->port = dpaa_intf->ifid;
+
+ mbuf->nb_segs = 1;
+ mbuf->ol_flags = 0;
+ mbuf->next = NULL;
+ rte_mbuf_refcnt_set(mbuf, 1);
+ dpaa_eth_packet_info(mbuf, mbuf->buf_addr);
+ dpaa_display_frame_info(fd, fq[0]->fqid, true);
+ }
+}
+
+void
+dpaa_rx_cb(struct qman_fq **fq, struct qm_dqrr_entry **dqrr,
+ void **bufs, int num_bufs)
+{
+ struct rte_mbuf *mbuf;
+ const struct qm_fd *fd;
+ struct dpaa_if *dpaa_intf;
+ uint16_t offset, i;
+ uint32_t length;
+ uint8_t format;
+
+ for (i = 0; i < num_bufs; i++) {
+ fd = &dqrr[i]->fd;
+ dpaa_intf = fq[0]->dpaa_intf;
+ format = (fd->opaque & DPAA_FD_FORMAT_MASK) >>
+ DPAA_FD_FORMAT_SHIFT;
+ if (unlikely(format == qm_fd_sg)) {
+ bufs[i] = dpaa_eth_sg_to_mbuf(fd, dpaa_intf->ifid);
+ continue;
+ }
+
+ offset = (fd->opaque & DPAA_FD_OFFSET_MASK) >>
+ DPAA_FD_OFFSET_SHIFT;
+ length = fd->opaque & DPAA_FD_LENGTH_MASK;
+
+ mbuf = bufs[i];
+ mbuf->data_off = offset;
+ mbuf->data_len = length;
+ mbuf->pkt_len = length;
+ mbuf->port = dpaa_intf->ifid;
+
+ mbuf->nb_segs = 1;
+ mbuf->ol_flags = 0;
+ mbuf->next = NULL;
+ rte_mbuf_refcnt_set(mbuf, 1);
+ dpaa_eth_packet_info(mbuf, mbuf->buf_addr);
+ dpaa_display_frame_info(fd, fq[0]->fqid, true);
+ }
+}
+
+void dpaa_rx_cb_prepare(struct qm_dqrr_entry *dq, void **bufs)
+{
+ struct dpaa_bp_info *bp_info = DPAA_BPID_TO_POOL_INFO(dq->fd.bpid);
+ void *ptr = rte_dpaa_mem_ptov(qm_fd_addr(&dq->fd));
+
+ /* In case of LS1046, annotation stashing is disabled due to L2 cache
+ * being bottleneck in case of multicore scanario for this platform.
+ * So we prefetch the annoation beforehand, so that it is available
+ * in cache when accessed.
+ */
+ rte_prefetch0((void *)((uint8_t *)ptr + DEFAULT_RX_ICEOF));
+
+ *bufs = (struct rte_mbuf *)((char *)ptr - bp_info->meta_data_size);
+}
+
+static uint16_t
+dpaa_eth_queue_portal_rx(struct qman_fq *fq,
+ struct rte_mbuf **bufs,
+ uint16_t nb_bufs)
+{
+ int ret;
+
+ if (unlikely(!fq->qp_initialized)) {
+ ret = rte_dpaa_portal_fq_init((void *)0, fq);
+ if (ret) {
+ DPAA_PMD_ERR("Failure in affining portal %d", ret);
+ return 0;
+ }
+ fq->qp_initialized = 1;
+ }
+
+ return qman_portal_poll_rx(nb_bufs, (void **)bufs, fq->qp);
+}
+
+enum qman_cb_dqrr_result
+dpaa_rx_cb_parallel(void *event,
+ struct qman_portal *qm __always_unused,
+ struct qman_fq *fq,
+ const struct qm_dqrr_entry *dqrr,
+ void **bufs)
+{
+ u32 ifid = ((struct dpaa_if *)fq->dpaa_intf)->ifid;
+ struct rte_mbuf *mbuf;
+ struct rte_event *ev = (struct rte_event *)event;
+
+ mbuf = dpaa_eth_fd_to_mbuf(&dqrr->fd, ifid);
+ ev->event_ptr = (void *)mbuf;
+ ev->flow_id = fq->ev.flow_id;
+ ev->sub_event_type = fq->ev.sub_event_type;
+ ev->event_type = RTE_EVENT_TYPE_ETHDEV;
+ ev->op = RTE_EVENT_OP_NEW;
+ ev->sched_type = fq->ev.sched_type;
+ ev->queue_id = fq->ev.queue_id;
+ ev->priority = fq->ev.priority;
+ ev->impl_opaque = (uint8_t)DPAA_INVALID_MBUF_SEQN;
+ mbuf->seqn = DPAA_INVALID_MBUF_SEQN;
+ *bufs = mbuf;
+
+ return qman_cb_dqrr_consume;
+}
+
+enum qman_cb_dqrr_result
+dpaa_rx_cb_atomic(void *event,
+ struct qman_portal *qm __always_unused,
+ struct qman_fq *fq,
+ const struct qm_dqrr_entry *dqrr,
+ void **bufs)
+{
+ u8 index;
+ u32 ifid = ((struct dpaa_if *)fq->dpaa_intf)->ifid;
+ struct rte_mbuf *mbuf;
+ struct rte_event *ev = (struct rte_event *)event;
+
+ mbuf = dpaa_eth_fd_to_mbuf(&dqrr->fd, ifid);
+ ev->event_ptr = (void *)mbuf;
+ ev->flow_id = fq->ev.flow_id;
+ ev->sub_event_type = fq->ev.sub_event_type;
+ ev->event_type = RTE_EVENT_TYPE_ETHDEV;
+ ev->op = RTE_EVENT_OP_NEW;
+ ev->sched_type = fq->ev.sched_type;
+ ev->queue_id = fq->ev.queue_id;
+ ev->priority = fq->ev.priority;
+
+ /* Save active dqrr entries */
+ index = DQRR_PTR2IDX(dqrr);
+ DPAA_PER_LCORE_DQRR_SIZE++;
+ DPAA_PER_LCORE_DQRR_HELD |= 1 << index;
+ DPAA_PER_LCORE_DQRR_MBUF(index) = mbuf;
+ ev->impl_opaque = index + 1;
+ mbuf->seqn = (uint32_t)index + 1;
+ *bufs = mbuf;
+
+ return qman_cb_dqrr_defer;
+}
+
+#ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
+static inline void dpaa_eth_err_queue(struct dpaa_if *dpaa_intf)
+{
+ struct rte_mbuf *mbuf;
+ struct qman_fq *debug_fq;
+ int ret, i;
+ struct qm_dqrr_entry *dq;
+ struct qm_fd *fd;
+
+ if (unlikely(!RTE_PER_LCORE(dpaa_io))) {
+ ret = rte_dpaa_portal_init((void *)0);
+ if (ret) {
+ DPAA_PMD_ERR("Failure in affining portal");
+ return;
+ }
+ }
+ for (i = 0; i <= DPAA_DEBUG_FQ_TX_ERROR; i++) {
+ debug_fq = &dpaa_intf->debug_queues[i];
+ ret = qman_set_vdq(debug_fq, 4, QM_VDQCR_EXACT);
+ if (ret)
+ return;
+
+ do {
+ dq = qman_dequeue(debug_fq);
+ if (!dq)
+ continue;
+ fd = &dq->fd;
+ if (i == DPAA_DEBUG_FQ_RX_ERROR)
+ DPAA_PMD_ERR("RX ERROR status: 0x%08x",
+ fd->status);
+ else
+ DPAA_PMD_ERR("TX ERROR status: 0x%08x",
+ fd->status);
+ dpaa_display_frame_info(fd, debug_fq->fqid,
+ i == DPAA_DEBUG_FQ_RX_ERROR);
+
+ mbuf = dpaa_eth_fd_to_mbuf(fd, dpaa_intf->ifid);
+ rte_pktmbuf_free(mbuf);
+ qman_dqrr_consume(debug_fq, dq);
+ } while (debug_fq->flags & QMAN_FQ_STATE_VDQCR);
+ }
+}
+#endif
+