+ */
+
+#include <time.h>
+#include <net/if.h>
+
+#include <rte_mbuf.h>
+#include <rte_ethdev_driver.h>
+#include <rte_malloc.h>
+#include <rte_memcpy.h>
+#include <rte_string_fns.h>
+#include <rte_cycles.h>
+#include <rte_kvargs.h>
+#include <rte_dev.h>
+#include <rte_fslmc.h>
+#include <rte_flow_driver.h>
+
+#include "dpaa2_pmd_logs.h"
+#include <fslmc_vfio.h>
+#include <dpaa2_hw_pvt.h>
+#include <dpaa2_hw_mempool.h>
+#include <dpaa2_hw_dpio.h>
+#include <mc/fsl_dpmng.h>
+#include "dpaa2_ethdev.h"
+#include "dpaa2_sparser.h"
+#include <fsl_qbman_debug.h>
+
+#define DRIVER_LOOPBACK_MODE "drv_loopback"
+#define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
+
+/* Supported Rx offloads */
+static uint64_t dev_rx_offloads_sup =
+ DEV_RX_OFFLOAD_CHECKSUM |
+ DEV_RX_OFFLOAD_SCTP_CKSUM |
+ DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
+ DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
+ DEV_RX_OFFLOAD_VLAN_STRIP |
+ DEV_RX_OFFLOAD_VLAN_FILTER |
+ DEV_RX_OFFLOAD_JUMBO_FRAME |
+ DEV_RX_OFFLOAD_TIMESTAMP;
+
+/* Rx offloads which cannot be disabled */
+static uint64_t dev_rx_offloads_nodis =
+ DEV_RX_OFFLOAD_RSS_HASH |
+ DEV_RX_OFFLOAD_SCATTER;
+
+/* Supported Tx offloads */
+static uint64_t dev_tx_offloads_sup =
+ DEV_TX_OFFLOAD_VLAN_INSERT |
+ DEV_TX_OFFLOAD_IPV4_CKSUM |
+ DEV_TX_OFFLOAD_UDP_CKSUM |
+ DEV_TX_OFFLOAD_TCP_CKSUM |
+ DEV_TX_OFFLOAD_SCTP_CKSUM |
+ DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
+ DEV_TX_OFFLOAD_MT_LOCKFREE |
+ DEV_TX_OFFLOAD_MBUF_FAST_FREE;
+
+/* Tx offloads which cannot be disabled */
+static uint64_t dev_tx_offloads_nodis =
+ DEV_TX_OFFLOAD_MULTI_SEGS;
+
+/* enable timestamp in mbuf */
+bool dpaa2_enable_ts;
+
+struct rte_dpaa2_xstats_name_off {
+ char name[RTE_ETH_XSTATS_NAME_SIZE];
+ uint8_t page_id; /* dpni statistics page id */
+ uint8_t stats_id; /* stats id in the given page */
+};
+
+static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
+ {"ingress_multicast_frames", 0, 2},
+ {"ingress_multicast_bytes", 0, 3},
+ {"ingress_broadcast_frames", 0, 4},
+ {"ingress_broadcast_bytes", 0, 5},
+ {"egress_multicast_frames", 1, 2},
+ {"egress_multicast_bytes", 1, 3},
+ {"egress_broadcast_frames", 1, 4},
+ {"egress_broadcast_bytes", 1, 5},
+ {"ingress_filtered_frames", 2, 0},
+ {"ingress_discarded_frames", 2, 1},
+ {"ingress_nobuffer_discards", 2, 2},
+ {"egress_discarded_frames", 2, 3},
+ {"egress_confirmed_frames", 2, 4},
+ {"cgr_reject_frames", 4, 0},
+ {"cgr_reject_bytes", 4, 1},
+};
+
+static const enum rte_filter_op dpaa2_supported_filter_ops[] = {
+ RTE_ETH_FILTER_ADD,
+ RTE_ETH_FILTER_DELETE,
+ RTE_ETH_FILTER_UPDATE,
+ RTE_ETH_FILTER_FLUSH,
+ RTE_ETH_FILTER_GET
+};
+
+static struct rte_dpaa2_driver rte_dpaa2_pmd;
+static int dpaa2_dev_uninit(struct rte_eth_dev *eth_dev);
+static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
+ int wait_to_complete);
+static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
+static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
+static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
+
+static int
+dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
+{
+ int ret;
+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
+ struct fsl_mc_io *dpni = dev->process_private;
+
+ PMD_INIT_FUNC_TRACE();
+
+ if (dpni == NULL) {
+ DPAA2_PMD_ERR("dpni is NULL");
+ return -1;
+ }
+
+ if (on)
+ ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
+ vlan_id, 0, 0, 0);
+ else
+ ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
+ priv->token, vlan_id);
+
+ if (ret < 0)
+ DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
+ ret, vlan_id, priv->hw_id);
+
+ return ret;
+}
+
+static int
+dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
+{
+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
+ struct fsl_mc_io *dpni = dev->process_private;
+ int ret = 0;
+
+ PMD_INIT_FUNC_TRACE();
+
+ if (mask & ETH_VLAN_FILTER_MASK) {
+ /* VLAN Filter not avaialble */
+ if (!priv->max_vlan_filters) {
+ DPAA2_PMD_INFO("VLAN filter not available");
+ return -ENOTSUP;
+ }
+
+ if (dev->data->dev_conf.rxmode.offloads &
+ DEV_RX_OFFLOAD_VLAN_FILTER)
+ ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
+ priv->token, true);
+ else
+ ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
+ priv->token, false);
+ if (ret < 0)
+ DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
+ }
+
+ return ret;
+}
+
+static int
+dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
+ enum rte_vlan_type vlan_type __rte_unused,
+ uint16_t tpid)
+{
+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
+ struct fsl_mc_io *dpni = dev->process_private;
+ int ret = -ENOTSUP;
+
+ PMD_INIT_FUNC_TRACE();
+
+ /* nothing to be done for standard vlan tpids */
+ if (tpid == 0x8100 || tpid == 0x88A8)
+ return 0;
+
+ ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
+ priv->token, tpid);
+ if (ret < 0)
+ DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
+ /* if already configured tpids, remove them first */
+ if (ret == -EBUSY) {
+ struct dpni_custom_tpid_cfg tpid_list = {0};
+
+ ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
+ priv->token, &tpid_list);
+ if (ret < 0)
+ goto fail;
+ ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
+ priv->token, tpid_list.tpid1);
+ if (ret < 0)
+ goto fail;
+ ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
+ priv->token, tpid);
+ }
+fail:
+ return ret;
+}
+
+static int
+dpaa2_fw_version_get(struct rte_eth_dev *dev,
+ char *fw_version,
+ size_t fw_size)
+{
+ int ret;
+ struct fsl_mc_io *dpni = dev->process_private;
+ struct mc_soc_version mc_plat_info = {0};
+ struct mc_version mc_ver_info = {0};
+
+ PMD_INIT_FUNC_TRACE();
+
+ if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
+ DPAA2_PMD_WARN("\tmc_get_soc_version failed");
+
+ if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
+ DPAA2_PMD_WARN("\tmc_get_version failed");
+
+ ret = snprintf(fw_version, fw_size,
+ "%x-%d.%d.%d",
+ mc_plat_info.svr,
+ mc_ver_info.major,
+ mc_ver_info.minor,
+ mc_ver_info.revision);
+
+ ret += 1; /* add the size of '\0' */
+ if (fw_size < (uint32_t)ret)
+ return ret;
+ else
+ return 0;
+}
+
+static int
+dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
+{
+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
+
+ PMD_INIT_FUNC_TRACE();
+
+ dev_info->if_index = priv->hw_id;
+
+ dev_info->max_mac_addrs = priv->max_mac_filters;
+ dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
+ dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
+ dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
+ dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
+ dev_info->rx_offload_capa = dev_rx_offloads_sup |
+ dev_rx_offloads_nodis;
+ dev_info->tx_offload_capa = dev_tx_offloads_sup |
+ dev_tx_offloads_nodis;
+ dev_info->speed_capa = ETH_LINK_SPEED_1G |
+ ETH_LINK_SPEED_2_5G |
+ ETH_LINK_SPEED_10G;
+
+ dev_info->max_hash_mac_addrs = 0;
+ dev_info->max_vfs = 0;
+ dev_info->max_vmdq_pools = ETH_16_POOLS;
+ dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
+
+ dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
+ /* same is rx size for best perf */
+ dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
+
+ dev_info->default_rxportconf.nb_queues = 1;
+ dev_info->default_txportconf.nb_queues = 1;
+ dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
+ dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
+
+ if (dpaa2_svr_family == SVR_LX2160A) {
+ dev_info->speed_capa |= ETH_LINK_SPEED_25G |
+ ETH_LINK_SPEED_40G |
+ ETH_LINK_SPEED_50G |
+ ETH_LINK_SPEED_100G;
+ }
+
+ return 0;
+}
+
+static int
+dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
+{
+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
+ uint16_t dist_idx;
+ uint32_t vq_id;
+ uint8_t num_rxqueue_per_tc;
+ struct dpaa2_queue *mc_q, *mcq;
+ uint32_t tot_queues;
+ int i;
+ struct dpaa2_queue *dpaa2_q;
+
+ PMD_INIT_FUNC_TRACE();
+
+ num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
+ if (priv->tx_conf_en)
+ tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
+ else
+ tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
+ mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
+ RTE_CACHE_LINE_SIZE);
+ if (!mc_q) {
+ DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
+ return -1;
+ }
+
+ for (i = 0; i < priv->nb_rx_queues; i++) {
+ mc_q->eth_data = dev->data;
+ priv->rx_vq[i] = mc_q++;
+ dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
+ dpaa2_q->q_storage = rte_malloc("dq_storage",
+ sizeof(struct queue_storage_info_t),
+ RTE_CACHE_LINE_SIZE);
+ if (!dpaa2_q->q_storage)
+ goto fail;
+
+ memset(dpaa2_q->q_storage, 0,
+ sizeof(struct queue_storage_info_t));
+ if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
+ goto fail;
+ }
+
+ for (i = 0; i < priv->nb_tx_queues; i++) {
+ mc_q->eth_data = dev->data;
+ mc_q->flow_id = 0xffff;
+ priv->tx_vq[i] = mc_q++;
+ dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
+ dpaa2_q->cscn = rte_malloc(NULL,
+ sizeof(struct qbman_result), 16);
+ if (!dpaa2_q->cscn)
+ goto fail_tx;
+ }
+
+ if (priv->tx_conf_en) {
+ /*Setup tx confirmation queues*/
+ for (i = 0; i < priv->nb_tx_queues; i++) {
+ mc_q->eth_data = dev->data;
+ mc_q->tc_index = i;
+ mc_q->flow_id = 0;
+ priv->tx_conf_vq[i] = mc_q++;
+ dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
+ dpaa2_q->q_storage =
+ rte_malloc("dq_storage",
+ sizeof(struct queue_storage_info_t),
+ RTE_CACHE_LINE_SIZE);
+ if (!dpaa2_q->q_storage)
+ goto fail_tx_conf;
+
+ memset(dpaa2_q->q_storage, 0,
+ sizeof(struct queue_storage_info_t));
+ if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
+ goto fail_tx_conf;
+ }
+ }
+
+ vq_id = 0;
+ for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
+ mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
+ mcq->tc_index = dist_idx / num_rxqueue_per_tc;
+ mcq->flow_id = dist_idx % num_rxqueue_per_tc;
+ vq_id++;
+ }
+
+ return 0;
+fail_tx_conf:
+ i -= 1;
+ while (i >= 0) {
+ dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
+ rte_free(dpaa2_q->q_storage);
+ priv->tx_conf_vq[i--] = NULL;
+ }
+ i = priv->nb_tx_queues;
+fail_tx:
+ i -= 1;
+ while (i >= 0) {
+ dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
+ rte_free(dpaa2_q->cscn);
+ priv->tx_vq[i--] = NULL;
+ }
+ i = priv->nb_rx_queues;
+fail:
+ i -= 1;
+ mc_q = priv->rx_vq[0];
+ while (i >= 0) {
+ dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
+ dpaa2_free_dq_storage(dpaa2_q->q_storage);
+ rte_free(dpaa2_q->q_storage);
+ priv->rx_vq[i--] = NULL;
+ }
+ rte_free(mc_q);
+ return -1;
+}
+
+static void
+dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
+{
+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
+ struct dpaa2_queue *dpaa2_q;
+ int i;
+
+ PMD_INIT_FUNC_TRACE();
+
+ /* Queue allocation base */
+ if (priv->rx_vq[0]) {
+ /* cleaning up queue storage */
+ for (i = 0; i < priv->nb_rx_queues; i++) {
+ dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
+ if (dpaa2_q->q_storage)
+ rte_free(dpaa2_q->q_storage);
+ }
+ /* cleanup tx queue cscn */
+ for (i = 0; i < priv->nb_tx_queues; i++) {
+ dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
+ rte_free(dpaa2_q->cscn);
+ }
+ if (priv->tx_conf_en) {
+ /* cleanup tx conf queue storage */
+ for (i = 0; i < priv->nb_tx_queues; i++) {
+ dpaa2_q = (struct dpaa2_queue *)
+ priv->tx_conf_vq[i];
+ rte_free(dpaa2_q->q_storage);
+ }
+ }
+ /*free memory for all queues (RX+TX) */
+ rte_free(priv->rx_vq[0]);
+ priv->rx_vq[0] = NULL;
+ }
+}
+
+static int
+dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
+{
+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
+ struct fsl_mc_io *dpni = dev->process_private;
+ struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
+ uint64_t rx_offloads = eth_conf->rxmode.offloads;
+ uint64_t tx_offloads = eth_conf->txmode.offloads;
+ int rx_l3_csum_offload = false;
+ int rx_l4_csum_offload = false;
+ int tx_l3_csum_offload = false;
+ int tx_l4_csum_offload = false;
+ int ret, tc_index;
+
+ PMD_INIT_FUNC_TRACE();
+
+ /* Rx offloads which are enabled by default */
+ if (dev_rx_offloads_nodis & ~rx_offloads) {
+ DPAA2_PMD_INFO(
+ "Some of rx offloads enabled by default - requested 0x%" PRIx64
+ " fixed are 0x%" PRIx64,
+ rx_offloads, dev_rx_offloads_nodis);
+ }
+
+ /* Tx offloads which are enabled by default */
+ if (dev_tx_offloads_nodis & ~tx_offloads) {
+ DPAA2_PMD_INFO(
+ "Some of tx offloads enabled by default - requested 0x%" PRIx64
+ " fixed are 0x%" PRIx64,
+ tx_offloads, dev_tx_offloads_nodis);
+ }
+
+ if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
+ if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
+ ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
+ priv->token, eth_conf->rxmode.max_rx_pkt_len
+ - RTE_ETHER_CRC_LEN);
+ if (ret) {
+ DPAA2_PMD_ERR(
+ "Unable to set mtu. check config");
+ return ret;
+ }
+ dev->data->mtu =
+ dev->data->dev_conf.rxmode.max_rx_pkt_len -
+ RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN -
+ VLAN_TAG_SIZE;
+ } else {
+ return -1;
+ }
+ }
+
+ if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
+ for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
+ ret = dpaa2_setup_flow_dist(dev,
+ eth_conf->rx_adv_conf.rss_conf.rss_hf,
+ tc_index);
+ if (ret) {
+ DPAA2_PMD_ERR(
+ "Unable to set flow distribution on tc%d."
+ "Check queue config", tc_index);
+ return ret;
+ }
+ }
+ }
+
+ if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
+ rx_l3_csum_offload = true;
+
+ if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
+ (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) ||
+ (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM))
+ rx_l4_csum_offload = true;
+
+ ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
+ DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
+ if (ret) {
+ DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
+ return ret;
+ }
+
+ ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
+ DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
+ if (ret) {
+ DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
+ return ret;
+ }
+
+#if !defined(RTE_LIBRTE_IEEE1588)
+ if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
+#endif
+ dpaa2_enable_ts = true;
+
+ if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
+ tx_l3_csum_offload = true;
+
+ if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) ||
+ (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
+ (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM))
+ tx_l4_csum_offload = true;
+
+ ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
+ DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
+ if (ret) {
+ DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
+ return ret;
+ }
+
+ ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
+ DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
+ if (ret) {
+ DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
+ return ret;
+ }
+
+ /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
+ * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
+ * to 0 for LS2 in the hardware thus disabling data/annotation
+ * stashing. For LX2 this is fixed in hardware and thus hash result and
+ * parse results can be received in FD using this option.
+ */
+ if (dpaa2_svr_family == SVR_LX2160A) {
+ ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
+ DPNI_FLCTYPE_HASH, true);
+ if (ret) {
+ DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
+ return ret;
+ }
+ }
+
+ if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
+ dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
+
+ return 0;
+}
+
+/* Function to setup RX flow information. It contains traffic class ID,
+ * flow ID, destination configuration etc.
+ */
+static int
+dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
+ uint16_t rx_queue_id,
+ uint16_t nb_rx_desc,
+ unsigned int socket_id __rte_unused,
+ const struct rte_eth_rxconf *rx_conf __rte_unused,
+ struct rte_mempool *mb_pool)
+{
+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
+ struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
+ struct dpaa2_queue *dpaa2_q;
+ struct dpni_queue cfg;
+ uint8_t options = 0;
+ uint8_t flow_id;
+ uint32_t bpid;
+ int i, ret;
+
+ PMD_INIT_FUNC_TRACE();
+
+ DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
+ dev, rx_queue_id, mb_pool, rx_conf);
+
+ if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
+ bpid = mempool_to_bpid(mb_pool);
+ ret = dpaa2_attach_bp_list(priv,
+ rte_dpaa2_bpid_info[bpid].bp_list);
+ if (ret)
+ return ret;
+ }
+ dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
+ dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
+ dpaa2_q->bp_array = rte_dpaa2_bpid_info;
+
+ /*Get the flow id from given VQ id*/
+ flow_id = dpaa2_q->flow_id;
+ memset(&cfg, 0, sizeof(struct dpni_queue));
+
+ options = options | DPNI_QUEUE_OPT_USER_CTX;
+ cfg.user_context = (size_t)(dpaa2_q);
+
+ /* check if a private cgr available. */
+ for (i = 0; i < priv->max_cgs; i++) {
+ if (!priv->cgid_in_use[i]) {
+ priv->cgid_in_use[i] = 1;
+ break;
+ }
+ }
+
+ if (i < priv->max_cgs) {
+ options |= DPNI_QUEUE_OPT_SET_CGID;
+ cfg.cgid = i;
+ dpaa2_q->cgid = cfg.cgid;
+ } else {
+ dpaa2_q->cgid = 0xff;
+ }
+
+ /*if ls2088 or rev2 device, enable the stashing */
+
+ if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
+ options |= DPNI_QUEUE_OPT_FLC;
+ cfg.flc.stash_control = true;
+ cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
+ /* 00 00 00 - last 6 bit represent annotation, context stashing,
+ * data stashing setting 01 01 00 (0x14)
+ * (in following order ->DS AS CS)
+ * to enable 1 line data, 1 line annotation.
+ * For LX2, this setting should be 01 00 00 (0x10)
+ */
+ if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
+ cfg.flc.value |= 0x10;
+ else
+ cfg.flc.value |= 0x14;
+ }
+ ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
+ dpaa2_q->tc_index, flow_id, options, &cfg);
+ if (ret) {
+ DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
+ return -1;
+ }
+
+ if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
+ struct dpni_taildrop taildrop;
+
+ taildrop.enable = 1;
+
+ /* Private CGR will use tail drop length as nb_rx_desc.
+ * for rest cases we can use standard byte based tail drop.
+ * There is no HW restriction, but number of CGRs are limited,
+ * hence this restriction is placed.
+ */
+ if (dpaa2_q->cgid != 0xff) {
+ /*enabling per rx queue congestion control */
+ taildrop.threshold = nb_rx_desc;
+ taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
+ taildrop.oal = 0;
+ DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
+ rx_queue_id);
+ ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
+ DPNI_CP_CONGESTION_GROUP,
+ DPNI_QUEUE_RX,
+ dpaa2_q->tc_index,
+ dpaa2_q->cgid, &taildrop);
+ } else {
+ /*enabling per rx queue congestion control */
+ taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
+ taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
+ taildrop.oal = CONG_RX_OAL;
+ DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
+ rx_queue_id);
+ ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
+ DPNI_CP_QUEUE, DPNI_QUEUE_RX,
+ dpaa2_q->tc_index, flow_id,
+ &taildrop);
+ }
+ if (ret) {
+ DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
+ ret);
+ return -1;
+ }
+ } else { /* Disable tail Drop */
+ struct dpni_taildrop taildrop = {0};
+ DPAA2_PMD_INFO("Tail drop is disabled on queue");
+
+ taildrop.enable = 0;
+ if (dpaa2_q->cgid != 0xff) {
+ ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
+ DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
+ dpaa2_q->tc_index,
+ dpaa2_q->cgid, &taildrop);
+ } else {
+ ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
+ DPNI_CP_QUEUE, DPNI_QUEUE_RX,
+ dpaa2_q->tc_index, flow_id, &taildrop);
+ }
+ if (ret) {
+ DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
+ ret);
+ return -1;
+ }
+ }
+
+ dev->data->rx_queues[rx_queue_id] = dpaa2_q;
+ return 0;
+}
+
+static int
+dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
+ uint16_t tx_queue_id,
+ uint16_t nb_tx_desc __rte_unused,
+ unsigned int socket_id __rte_unused,
+ const struct rte_eth_txconf *tx_conf __rte_unused)
+{
+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
+ struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
+ priv->tx_vq[tx_queue_id];
+ struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
+ priv->tx_conf_vq[tx_queue_id];
+ struct fsl_mc_io *dpni = dev->process_private;
+ struct dpni_queue tx_conf_cfg;
+ struct dpni_queue tx_flow_cfg;
+ uint8_t options = 0, flow_id;
+ struct dpni_queue_id qid;
+ uint32_t tc_id;
+ int ret;
+
+ PMD_INIT_FUNC_TRACE();
+
+ /* Return if queue already configured */
+ if (dpaa2_q->flow_id != 0xffff) {
+ dev->data->tx_queues[tx_queue_id] = dpaa2_q;
+ return 0;
+ }
+
+ memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
+ memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
+
+ tc_id = tx_queue_id;
+ flow_id = 0;
+
+ ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
+ tc_id, flow_id, options, &tx_flow_cfg);
+ if (ret) {
+ DPAA2_PMD_ERR("Error in setting the tx flow: "
+ "tc_id=%d, flow=%d err=%d",
+ tc_id, flow_id, ret);
+ return -1;
+ }
+
+ dpaa2_q->flow_id = flow_id;
+
+ if (tx_queue_id == 0) {
+ /*Set tx-conf and error configuration*/
+ if (priv->tx_conf_en)
+ ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
+ priv->token,
+ DPNI_CONF_AFFINE);
+ else
+ ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
+ priv->token,
+ DPNI_CONF_DISABLE);
+ if (ret) {
+ DPAA2_PMD_ERR("Error in set tx conf mode settings: "
+ "err=%d", ret);
+ return -1;
+ }
+ }
+ dpaa2_q->tc_index = tc_id;
+
+ ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
+ DPNI_QUEUE_TX, dpaa2_q->tc_index,
+ dpaa2_q->flow_id, &tx_flow_cfg, &qid);
+ if (ret) {
+ DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
+ return -1;
+ }
+ dpaa2_q->fqid = qid.fqid;
+
+ if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
+ struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
+
+ cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
+ cong_notif_cfg.threshold_entry = CONG_ENTER_TX_THRESHOLD;
+ /* Notify that the queue is not congested when the data in
+ * the queue is below this thershold.
+ */
+ cong_notif_cfg.threshold_exit = CONG_EXIT_TX_THRESHOLD;
+ cong_notif_cfg.message_ctx = 0;
+ cong_notif_cfg.message_iova =
+ (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
+ cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
+ cong_notif_cfg.notification_mode =
+ DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
+ DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
+ DPNI_CONG_OPT_COHERENT_WRITE;
+ cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
+
+ ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
+ priv->token,
+ DPNI_QUEUE_TX,
+ tc_id,
+ &cong_notif_cfg);
+ if (ret) {
+ DPAA2_PMD_ERR(
+ "Error in setting tx congestion notification: "
+ "err=%d", ret);
+ return -ret;
+ }
+ }
+ dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
+ dev->data->tx_queues[tx_queue_id] = dpaa2_q;
+
+ if (priv->tx_conf_en) {
+ dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
+ options = options | DPNI_QUEUE_OPT_USER_CTX;
+ tx_conf_cfg.user_context = (size_t)(dpaa2_q);
+ ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
+ DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
+ dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
+ if (ret) {
+ DPAA2_PMD_ERR("Error in setting the tx conf flow: "
+ "tc_index=%d, flow=%d err=%d",
+ dpaa2_tx_conf_q->tc_index,
+ dpaa2_tx_conf_q->flow_id, ret);
+ return -1;
+ }
+
+ ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
+ DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
+ dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
+ if (ret) {
+ DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
+ return -1;
+ }
+ dpaa2_tx_conf_q->fqid = qid.fqid;
+ }
+ return 0;
+}
+
+static void
+dpaa2_dev_rx_queue_release(void *q __rte_unused)
+{
+ struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q;
+ struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
+ struct fsl_mc_io *dpni =
+ (struct fsl_mc_io *)priv->eth_dev->process_private;
+ uint8_t options = 0;
+ int ret;
+ struct dpni_queue cfg;
+
+ memset(&cfg, 0, sizeof(struct dpni_queue));
+ PMD_INIT_FUNC_TRACE();
+ if (dpaa2_q->cgid != 0xff) {
+ options = DPNI_QUEUE_OPT_CLEAR_CGID;
+ cfg.cgid = dpaa2_q->cgid;
+
+ ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
+ DPNI_QUEUE_RX,
+ dpaa2_q->tc_index, dpaa2_q->flow_id,
+ options, &cfg);
+ if (ret)
+ DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
+ dpaa2_q->fqid, ret);
+ priv->cgid_in_use[dpaa2_q->cgid] = 0;
+ dpaa2_q->cgid = 0xff;
+ }
+}
+
+static void
+dpaa2_dev_tx_queue_release(void *q __rte_unused)
+{
+ PMD_INIT_FUNC_TRACE();
+}
+
+static uint32_t
+dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
+{
+ int32_t ret;
+ struct dpaa2_dev_priv *priv = dev->data->dev_private;
+ struct dpaa2_queue *dpaa2_q;
+ struct qbman_swp *swp;
+ struct qbman_fq_query_np_rslt state;
+ uint32_t frame_cnt = 0;
+
+ if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
+ ret = dpaa2_affine_qbman_swp();
+ if (ret) {
+ DPAA2_PMD_ERR(
+ "Failed to allocate IO portal, tid: %d\n",
+ rte_gettid());
+ return -EINVAL;
+ }
+ }
+ swp = DPAA2_PER_LCORE_PORTAL;
+
+ dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
+
+ if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
+ frame_cnt = qbman_fq_state_frame_count(&state);
+ DPAA2_PMD_DP_DEBUG("RX frame count for q(%d) is %u",
+ rx_queue_id, frame_cnt);
+ }
+ return frame_cnt;
+}
+
+static const uint32_t *
+dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
+{
+ static const uint32_t ptypes[] = {
+ /*todo -= add more types */
+ RTE_PTYPE_L2_ETHER,
+ RTE_PTYPE_L3_IPV4,
+ RTE_PTYPE_L3_IPV4_EXT,
+ RTE_PTYPE_L3_IPV6,
+ RTE_PTYPE_L3_IPV6_EXT,
+ RTE_PTYPE_L4_TCP,
+ RTE_PTYPE_L4_UDP,
+ RTE_PTYPE_L4_SCTP,
+ RTE_PTYPE_L4_ICMP,
+ RTE_PTYPE_UNKNOWN
+ };
+
+ if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
+ dev->rx_pkt_burst == dpaa2_dev_rx ||
+ dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
+ return ptypes;
+ return NULL;
+}
+
+/**
+ * Dpaa2 link Interrupt handler