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net/cnxk: enable PTP processing in vector Tx
[dpdk.git]
/
drivers
/
net
/
dpaa2
/
dpaa2_ethdev.h
diff --git
a/drivers/net/dpaa2/dpaa2_ethdev.h
b/drivers/net/dpaa2/dpaa2_ethdev.h
index
94cf253
..
7b76ca7
100644
(file)
--- a/
drivers/net/dpaa2/dpaa2_ethdev.h
+++ b/
drivers/net/dpaa2/dpaa2_ethdev.h
@@
-1,7
+1,7
@@
/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved.
/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved.
- * Copyright 2016-202
0
NXP
+ * Copyright 2016-202
1
NXP
*
*/
*
*/
@@
-12,6
+12,7
@@
#include <rte_pmd_dpaa2.h>
#include <dpaa2_hw_pvt.h>
#include <rte_pmd_dpaa2.h>
#include <dpaa2_hw_pvt.h>
+#include "dpaa2_tm.h"
#include <mc/fsl_dpni.h>
#include <mc/fsl_mc_sys.h>
#include <mc/fsl_dpni.h>
#include <mc/fsl_mc_sys.h>
@@
-26,6
+27,10
@@
#define DPAA2_RX_DEFAULT_NBDESC 512
#define DPAA2_RX_DEFAULT_NBDESC 512
+#define DPAA2_ETH_MAX_LEN (RTE_ETHER_MTU + \
+ RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \
+ VLAN_TAG_SIZE)
+
/*default tc to be used for ,congestion, distribution etc configuration. */
#define DPAA2_DEF_TC 0
/*default tc to be used for ,congestion, distribution etc configuration. */
#define DPAA2_DEF_TC 0
@@
-55,13
+60,16
@@
/* Disable RX tail drop, default is enable */
#define DPAA2_RX_TAILDROP_OFF 0x04
/* Disable RX tail drop, default is enable */
#define DPAA2_RX_TAILDROP_OFF 0x04
+/* Tx confirmation enabled */
+#define DPAA2_TX_CONF_ENABLE 0x08
#define DPAA2_RSS_OFFLOAD_ALL ( \
ETH_RSS_L2_PAYLOAD | \
ETH_RSS_IP | \
ETH_RSS_UDP | \
ETH_RSS_TCP | \
#define DPAA2_RSS_OFFLOAD_ALL ( \
ETH_RSS_L2_PAYLOAD | \
ETH_RSS_IP | \
ETH_RSS_UDP | \
ETH_RSS_TCP | \
- ETH_RSS_SCTP)
+ ETH_RSS_SCTP | \
+ ETH_RSS_MPLS)
/* LX2 FRC Parsed values (Little Endian) */
#define DPAA2_PKT_TYPE_ETHER 0x0060
/* LX2 FRC Parsed values (Little Endian) */
#define DPAA2_PKT_TYPE_ETHER 0x0060
@@
-92,6
+100,8
@@
/* enable timestamp in mbuf*/
extern bool dpaa2_enable_ts[];
/* enable timestamp in mbuf*/
extern bool dpaa2_enable_ts[];
+extern uint64_t dpaa2_timestamp_rx_dynflag;
+extern int dpaa2_timestamp_dynfield_offset;
#define DPAA2_QOS_TABLE_RECONFIGURE 1
#define DPAA2_FS_TABLE_RECONFIGURE 2
#define DPAA2_QOS_TABLE_RECONFIGURE 1
#define DPAA2_FS_TABLE_RECONFIGURE 2
@@
-103,7
+113,10
@@
extern bool dpaa2_enable_ts[];
/*Externaly defined*/
extern const struct rte_flow_ops dpaa2_flow_ops;
/*Externaly defined*/
extern const struct rte_flow_ops dpaa2_flow_ops;
-extern enum rte_filter_type dpaa2_filter_type;
+
+extern const struct rte_tm_ops dpaa2_tm_ops;
+
+extern bool dpaa2_enable_err_queue;
#define IP_ADDRESS_OFFSET_INVALID (-1)
#define IP_ADDRESS_OFFSET_INVALID (-1)
@@
-142,14
+155,14
@@
struct dpaa2_dev_priv {
void *tx_vq[MAX_TX_QUEUES];
struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */
void *tx_conf_vq[MAX_TX_QUEUES];
void *tx_vq[MAX_TX_QUEUES];
struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */
void *tx_conf_vq[MAX_TX_QUEUES];
- uint8_t tx_conf_en;
+ void *rx_err_vq;
+ uint8_t flags; /*dpaa2 config flags */
uint8_t max_mac_filters;
uint8_t max_vlan_filters;
uint8_t num_rx_tc;
uint16_t qos_entries;
uint16_t fs_entries;
uint8_t dist_queues;
uint8_t max_mac_filters;
uint8_t max_vlan_filters;
uint8_t num_rx_tc;
uint16_t qos_entries;
uint16_t fs_entries;
uint8_t dist_queues;
- uint8_t flags; /*dpaa2 config flags */
uint8_t en_ordered;
uint8_t en_loose_ordered;
uint8_t max_cgs;
uint8_t en_ordered;
uint8_t en_loose_ordered;
uint8_t max_cgs;
@@
-172,6
+185,8
@@
struct dpaa2_dev_priv {
struct rte_eth_dev *eth_dev; /**< Pointer back to holding ethdev */
LIST_HEAD(, rte_flow) flows; /**< Configured flow rule handles. */
struct rte_eth_dev *eth_dev; /**< Pointer back to holding ethdev */
LIST_HEAD(, rte_flow) flows; /**< Configured flow rule handles. */
+ LIST_HEAD(nodes, dpaa2_tm_node) nodes;
+ LIST_HEAD(shaper_profiles, dpaa2_tm_shaper_profile) shaper_profiles;
};
int dpaa2_distset_to_dpkg_profile_cfg(uint64_t req_dist_set,
};
int dpaa2_distset_to_dpkg_profile_cfg(uint64_t req_dist_set,