+static uint64_t
+igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
+{
+ struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ uint64_t systime_cycles;
+
+ switch (hw->mac.type) {
+ case e1000_i210:
+ case e1000_i211:
+ /*
+ * Need to read System Time Residue Register to be able
+ * to read the other two registers.
+ */
+ E1000_READ_REG(hw, E1000_SYSTIMR);
+ /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
+ systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
+ systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
+ * NSEC_PER_SEC;
+ break;
+ case e1000_82580:
+ case e1000_i350:
+ case e1000_i354:
+ /*
+ * Need to read System Time Residue Register to be able
+ * to read the other two registers.
+ */
+ E1000_READ_REG(hw, E1000_SYSTIMR);
+ systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
+ /* Only the 8 LSB are valid. */
+ systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
+ & 0xff) << 32;
+ break;
+ default:
+ systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
+ systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
+ << 32;
+ break;
+ }
+
+ return systime_cycles;
+}
+
+static uint64_t
+igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
+{
+ struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ uint64_t rx_tstamp_cycles;
+
+ switch (hw->mac.type) {
+ case e1000_i210:
+ case e1000_i211:
+ /* RXSTMPL stores ns and RXSTMPH stores seconds. */
+ rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
+ rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
+ * NSEC_PER_SEC;
+ break;
+ case e1000_82580:
+ case e1000_i350:
+ case e1000_i354:
+ rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
+ /* Only the 8 LSB are valid. */
+ rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
+ & 0xff) << 32;
+ break;
+ default:
+ rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
+ rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
+ << 32;
+ break;
+ }
+
+ return rx_tstamp_cycles;
+}
+
+static uint64_t
+igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
+{
+ struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ uint64_t tx_tstamp_cycles;
+
+ switch (hw->mac.type) {
+ case e1000_i210:
+ case e1000_i211:
+ /* RXSTMPL stores ns and RXSTMPH stores seconds. */
+ tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
+ tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
+ * NSEC_PER_SEC;
+ break;
+ case e1000_82580:
+ case e1000_i350:
+ case e1000_i354:
+ tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
+ /* Only the 8 LSB are valid. */
+ tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
+ & 0xff) << 32;
+ break;
+ default:
+ tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
+ tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
+ << 32;
+ break;
+ }
+
+ return tx_tstamp_cycles;
+}
+
+static void
+igb_start_timecounters(struct rte_eth_dev *dev)
+{
+ struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct e1000_adapter *adapter =
+ (struct e1000_adapter *)dev->data->dev_private;
+ uint32_t incval = 1;
+ uint32_t shift = 0;
+ uint64_t mask = E1000_CYCLECOUNTER_MASK;
+
+ switch (hw->mac.type) {
+ case e1000_82580:
+ case e1000_i350:
+ case e1000_i354:
+ /* 32 LSB bits + 8 MSB bits = 40 bits */
+ mask = (1ULL << 40) - 1;
+ /* fall-through */
+ case e1000_i210:
+ case e1000_i211:
+ /*
+ * Start incrementing the register
+ * used to timestamp PTP packets.
+ */
+ E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
+ break;
+ case e1000_82576:
+ incval = E1000_INCVALUE_82576;
+ shift = IGB_82576_TSYNC_SHIFT;
+ E1000_WRITE_REG(hw, E1000_TIMINCA,
+ E1000_INCPERIOD_82576 | incval);
+ break;
+ default:
+ /* Not supported */
+ return;
+ }
+
+ memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
+ memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
+ memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
+
+ adapter->systime_tc.cc_mask = mask;
+ adapter->systime_tc.cc_shift = shift;
+ adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
+
+ adapter->rx_tstamp_tc.cc_mask = mask;
+ adapter->rx_tstamp_tc.cc_shift = shift;
+ adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
+
+ adapter->tx_tstamp_tc.cc_mask = mask;
+ adapter->tx_tstamp_tc.cc_shift = shift;
+ adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
+}
+
+static int
+igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
+{
+ struct e1000_adapter *adapter =
+ (struct e1000_adapter *)dev->data->dev_private;
+
+ adapter->systime_tc.nsec += delta;
+ adapter->rx_tstamp_tc.nsec += delta;
+ adapter->tx_tstamp_tc.nsec += delta;
+
+ return 0;
+}
+
+static int
+igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
+{
+ uint64_t ns;
+ struct e1000_adapter *adapter =
+ (struct e1000_adapter *)dev->data->dev_private;
+
+ ns = rte_timespec_to_ns(ts);
+
+ /* Set the timecounters to a new value. */
+ adapter->systime_tc.nsec = ns;
+ adapter->rx_tstamp_tc.nsec = ns;
+ adapter->tx_tstamp_tc.nsec = ns;
+
+ return 0;
+}
+
+static int
+igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
+{
+ uint64_t ns, systime_cycles;
+ struct e1000_adapter *adapter =
+ (struct e1000_adapter *)dev->data->dev_private;
+
+ systime_cycles = igb_read_systime_cyclecounter(dev);
+ ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
+ *ts = rte_ns_to_timespec(ns);
+
+ return 0;
+}
+