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net/hns3: add check for deferred start queue when rollback
[dpdk.git]
/
drivers
/
net
/
hns3
/
hns3_cmd.h
diff --git
a/drivers/net/hns3/hns3_cmd.h
b/drivers/net/hns3/hns3_cmd.h
index
944e3d6
..
f9addc6
100644
(file)
--- a/
drivers/net/hns3/hns3_cmd.h
+++ b/
drivers/net/hns3/hns3_cmd.h
@@
-162,6
+162,9
@@
enum hns3_opcode_type {
HNS3_OPC_TM_INTERNAL_CNT = 0x0851,
HNS3_OPC_TM_INTERNAL_STS_1 = 0x0852,
HNS3_OPC_TM_INTERNAL_CNT = 0x0851,
HNS3_OPC_TM_INTERNAL_STS_1 = 0x0852,
+ HNS3_OPC_TM_PORT_LIMIT_RATE = 0x0870,
+ HNS3_OPC_TM_TC_LIMIT_RATE = 0x0871,
+
/* Mailbox cmd */
HNS3_OPC_MBX_VF_TO_PF = 0x2001,
/* Mailbox cmd */
HNS3_OPC_MBX_VF_TO_PF = 0x2001,
@@
-312,6
+315,7
@@
enum HNS3_CAPS_BITS {
*/
HNS3_CAPS_FD_QUEUE_REGION_B = 2,
HNS3_CAPS_PTP_B,
*/
HNS3_CAPS_FD_QUEUE_REGION_B = 2,
HNS3_CAPS_PTP_B,
+ HNS3_CAPS_TX_PUSH_B = 6,
HNS3_CAPS_PHY_IMP_B = 7,
HNS3_CAPS_TQP_TXRX_INDEP_B,
HNS3_CAPS_HW_PAD_B,
HNS3_CAPS_PHY_IMP_B = 7,
HNS3_CAPS_TQP_TXRX_INDEP_B,
HNS3_CAPS_HW_PAD_B,
@@
-319,6
+323,16
@@
enum HNS3_CAPS_BITS {
HNS3_CAPS_UDP_TUNNEL_CSUM_B,
HNS3_CAPS_RAS_IMP_B,
HNS3_CAPS_RXD_ADV_LAYOUT_B = 15,
HNS3_CAPS_UDP_TUNNEL_CSUM_B,
HNS3_CAPS_RAS_IMP_B,
HNS3_CAPS_RXD_ADV_LAYOUT_B = 15,
+ HNS3_CAPS_TM_B = 17,
+};
+
+/* Capabilities of VF dependent on the PF */
+enum HNS3VF_CAPS_BITS {
+ /*
+ * The following capability index definitions must be the same as those
+ * in kernel side PF.
+ */
+ HNS3VF_CAPS_VLAN_FLT_MOD_B = 0,
};
enum HNS3_API_CAP_BITS {
};
enum HNS3_API_CAP_BITS {
@@
-457,8
+471,6
@@
struct hns3_umv_spc_alc_cmd {
#define HNS3_CFG_RD_LEN_BYTES 16
#define HNS3_CFG_RD_LEN_UNIT 4
#define HNS3_CFG_RD_LEN_BYTES 16
#define HNS3_CFG_RD_LEN_UNIT 4
-#define HNS3_CFG_VMDQ_S 0
-#define HNS3_CFG_VMDQ_M GENMASK(7, 0)
#define HNS3_CFG_TC_NUM_S 8
#define HNS3_CFG_TC_NUM_M GENMASK(15, 8)
#define HNS3_CFG_TQP_DESC_N_S 16
#define HNS3_CFG_TC_NUM_S 8
#define HNS3_CFG_TC_NUM_M GENMASK(15, 8)
#define HNS3_CFG_TQP_DESC_N_S 16
@@
-591,7
+603,6
@@
struct hns3_cfg_gro_status_cmd {
#define HNS3_RSS_HASH_KEY_OFFSET_B 4
#define HNS3_RSS_HASH_KEY_OFFSET_B 4
-#define HNS3_RSS_CFG_TBL_SIZE 16
#define HNS3_RSS_HASH_KEY_NUM 16
/* Configure the algorithm mode and Hash Key, opcode:0x0D01 */
struct hns3_rss_generic_config_cmd {
#define HNS3_RSS_HASH_KEY_NUM 16
/* Configure the algorithm mode and Hash Key, opcode:0x0D01 */
struct hns3_rss_generic_config_cmd {
@@
-911,7
+922,8
@@
enum hns3_mac_vlan_add_resp_code {
HNS3_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */
};
HNS3_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */
};
-#define HNS3_MC_MAC_VLAN_ADD_DESC_NUM 3
+#define HNS3_MC_MAC_VLAN_OPS_DESC_NUM 3
+#define HNS3_UC_MAC_VLAN_OPS_DESC_NUM 1
#define HNS3_MAC_VLAN_BIT0_EN_B 0
#define HNS3_MAC_VLAN_BIT1_EN_B 1
#define HNS3_MAC_VLAN_BIT0_EN_B 0
#define HNS3_MAC_VLAN_BIT1_EN_B 1