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net/hns3: support NEON Rx
[dpdk.git]
/
drivers
/
net
/
hns3
/
hns3_dcb.h
diff --git
a/drivers/net/hns3/hns3_dcb.h
b/drivers/net/hns3/hns3_dcb.h
index
9ec4e70
..
557d88b
100644
(file)
--- a/
drivers/net/hns3/hns3_dcb.h
+++ b/
drivers/net/hns3/hns3_dcb.h
@@
-5,6
+5,8
@@
#ifndef _HNS3_DCB_H_
#define _HNS3_DCB_H_
#ifndef _HNS3_DCB_H_
#define _HNS3_DCB_H_
+#define HNS3_ETHER_MAX_RATE 100000
+
/* MAC Pause */
#define HNS3_TX_MAC_PAUSE_EN_MSK BIT(0)
#define HNS3_RX_MAC_PAUSE_EN_MSK BIT(1)
/* MAC Pause */
#define HNS3_TX_MAC_PAUSE_EN_MSK BIT(0)
#define HNS3_RX_MAC_PAUSE_EN_MSK BIT(1)
@@
-24,16
+26,19
@@
enum hns3_shap_bucket {
struct hns3_priority_weight_cmd {
uint8_t pri_id;
uint8_t dwrr;
struct hns3_priority_weight_cmd {
uint8_t pri_id;
uint8_t dwrr;
+ uint8_t rsvd[22];
};
struct hns3_qs_weight_cmd {
uint16_t qs_id;
uint8_t dwrr;
};
struct hns3_qs_weight_cmd {
uint16_t qs_id;
uint8_t dwrr;
+ uint8_t rsvd[21];
};
struct hns3_pg_weight_cmd {
uint8_t pg_id;
uint8_t dwrr;
};
struct hns3_pg_weight_cmd {
uint8_t pg_id;
uint8_t dwrr;
+ uint8_t rsvd[22];
};
struct hns3_ets_tc_weight_cmd {
};
struct hns3_ets_tc_weight_cmd {
@@
-48,6
+53,7
@@
struct hns3_qs_to_pri_link_cmd {
uint8_t priority;
#define HNS3_DCB_QS_PRI_LINK_VLD_MSK BIT(0)
uint8_t link_vld;
uint8_t priority;
#define HNS3_DCB_QS_PRI_LINK_VLD_MSK BIT(0)
uint8_t link_vld;
+ uint8_t rsvd1[18];
};
struct hns3_nq_to_qs_link_cmd {
};
struct hns3_nq_to_qs_link_cmd {
@@
-55,6
+61,7
@@
struct hns3_nq_to_qs_link_cmd {
uint16_t rsvd;
#define HNS3_DCB_Q_QS_LINK_VLD_MSK BIT(10)
uint16_t qset_id;
uint16_t rsvd;
#define HNS3_DCB_Q_QS_LINK_VLD_MSK BIT(10)
uint16_t qset_id;
+ uint8_t rsvd1[18];
};
#define HNS3_DCB_SHAP_IR_B_MSK GENMASK(7, 0)
};
#define HNS3_DCB_SHAP_IR_B_MSK GENMASK(7, 0)
@@
-72,12
+79,14
@@
struct hns3_pri_shapping_cmd {
uint8_t pri_id;
uint8_t rsvd[3];
uint32_t pri_shapping_para;
uint8_t pri_id;
uint8_t rsvd[3];
uint32_t pri_shapping_para;
+ uint32_t rsvd1[4];
};
struct hns3_pg_shapping_cmd {
uint8_t pg_id;
uint8_t rsvd[3];
uint32_t pg_shapping_para;
};
struct hns3_pg_shapping_cmd {
uint8_t pg_id;
uint8_t rsvd[3];
uint32_t pg_shapping_para;
+ uint32_t rsvd1[4];
};
#define HNS3_BP_GRP_NUM 32
};
#define HNS3_BP_GRP_NUM 32
@@
-90,16
+99,18
@@
struct hns3_bp_to_qs_map_cmd {
uint8_t rsvd[2];
uint8_t qs_group_id;
uint32_t qs_bit_map;
uint8_t rsvd[2];
uint8_t qs_group_id;
uint32_t qs_bit_map;
- uint32_t rsvd1;
+ uint32_t rsvd1
[4]
;
};
struct hns3_pfc_en_cmd {
uint8_t tx_rx_en_bitmap;
uint8_t pri_en_bitmap;
};
struct hns3_pfc_en_cmd {
uint8_t tx_rx_en_bitmap;
uint8_t pri_en_bitmap;
+ uint8_t rsvd[22];
};
struct hns3_port_shapping_cmd {
uint32_t port_shapping_para;
};
struct hns3_port_shapping_cmd {
uint32_t port_shapping_para;
+ uint32_t rsvd[5];
};
struct hns3_cfg_pause_param_cmd {
};
struct hns3_cfg_pause_param_cmd {
@@
-117,6
+128,7
@@
struct hns3_pg_to_pri_link_cmd {
uint8_t pg_id;
uint8_t rsvd1[3];
uint8_t pri_bit_map;
uint8_t pg_id;
uint8_t rsvd1[3];
uint8_t pri_bit_map;
+ uint8_t rsvd2[19];
};
enum hns3_shaper_level {
};
enum hns3_shaper_level {
@@
-159,7
+171,9
@@
hns3_fc_enable(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);
int
hns3_dcb_pfc_enable(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf);
int
hns3_dcb_pfc_enable(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf);
-void hns3_tc_queue_mapping_cfg(struct hns3_hw *hw);
+void hns3_set_rss_size(struct hns3_hw *hw, uint16_t nb_rx_q);
+
+void hns3_tc_queue_mapping_cfg(struct hns3_hw *hw, uint16_t nb_queue);
int hns3_dcb_cfg_update(struct hns3_adapter *hns);
int hns3_dcb_cfg_update(struct hns3_adapter *hns);