+static enum hns3_evt_cause
+hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
+ uint32_t *vec_val)
+{
+ struct hns3_hw *hw = &hns->hw;
+
+ __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
+ hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
+ *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
+ if (!is_delay) {
+ hw->reset.stats.imp_cnt++;
+ hns3_warn(hw, "IMP reset detected, clear reset status");
+ } else {
+ hns3_schedule_delayed_reset(hns);
+ hns3_warn(hw, "IMP reset detected, don't clear reset status");
+ }
+
+ return HNS3_VECTOR0_EVENT_RST;
+}
+
+static enum hns3_evt_cause
+hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
+ uint32_t *vec_val)
+{
+ struct hns3_hw *hw = &hns->hw;
+
+ __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
+ hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
+ *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
+ if (!is_delay) {
+ hw->reset.stats.global_cnt++;
+ hns3_warn(hw, "Global reset detected, clear reset status");
+ } else {
+ hns3_schedule_delayed_reset(hns);
+ hns3_warn(hw,
+ "Global reset detected, don't clear reset status");
+ }
+
+ return HNS3_VECTOR0_EVENT_RST;
+}
+