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net/hns3: remove unused macros
[dpdk.git]
/
drivers
/
net
/
hns3
/
hns3_ethdev.h
diff --git
a/drivers/net/hns3/hns3_ethdev.h
b/drivers/net/hns3/hns3_ethdev.h
index
7b7d359
..
b2dacb9
100644
(file)
--- a/
drivers/net/hns3/hns3_ethdev.h
+++ b/
drivers/net/hns3/hns3_ethdev.h
@@
-5,6
+5,7
@@
#ifndef _HNS3_ETHDEV_H_
#define _HNS3_ETHDEV_H_
#ifndef _HNS3_ETHDEV_H_
#define _HNS3_ETHDEV_H_
+#include <pthread.h>
#include <sys/time.h>
#include <ethdev_driver.h>
#include <rte_byteorder.h>
#include <sys/time.h>
#include <ethdev_driver.h>
#include <rte_byteorder.h>
@@
-41,6
+42,9
@@
#define HNS3_PF_FUNC_ID 0
#define HNS3_1ST_VF_FUNC_ID 1
#define HNS3_PF_FUNC_ID 0
#define HNS3_1ST_VF_FUNC_ID 1
+#define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
+#define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
+
#define HNS3_SW_SHIFT_AND_DISCARD_MODE 0
#define HNS3_HW_SHIFT_AND_DISCARD_MODE 1
#define HNS3_SW_SHIFT_AND_DISCARD_MODE 0
#define HNS3_HW_SHIFT_AND_DISCARD_MODE 1
@@
-306,8
+310,9
@@
enum hns3_reset_stage {
};
enum hns3_reset_level {
};
enum hns3_reset_level {
- HNS3_
NONE_RESET,
+ HNS3_
FLR_RESET, /* A VF perform FLR reset */
HNS3_VF_FUNC_RESET, /* A VF function reset */
HNS3_VF_FUNC_RESET, /* A VF function reset */
+
/*
* All VFs under a PF perform function reset.
* Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
/*
* All VFs under a PF perform function reset.
* Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
@@
-315,6
+320,7
@@
enum hns3_reset_level {
* same.
*/
HNS3_VF_PF_FUNC_RESET = 2,
* same.
*/
HNS3_VF_PF_FUNC_RESET = 2,
+
/*
* All VFs under a PF perform FLR reset.
* Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
/*
* All VFs under a PF perform FLR reset.
* Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
@@
-328,14
+334,23
@@
enum hns3_reset_level {
* In PF FLR, the register state of VF is not reliable, VF's driver
* should not access the registers of the VF device.
*/
* In PF FLR, the register state of VF is not reliable, VF's driver
* should not access the registers of the VF device.
*/
- HNS3_VF_FULL_RESET
= 3
,
- HNS3_FLR_RESET, /* A VF perform FLR reset */
+ HNS3_VF_FULL_RESET,
+
/* All VFs under the rootport perform a global or IMP reset */
HNS3_VF_RESET,
/* All VFs under the rootport perform a global or IMP reset */
HNS3_VF_RESET,
- HNS3_FUNC_RESET, /* A PF function reset */
+
+ /*
+ * The enumeration value of HNS3_FUNC_RESET/HNS3_GLOBAL_RESET/
+ * HNS3_IMP_RESET/HNS3_NONE_RESET are also used by firmware, and
+ * can not be changed.
+ */
+
+ HNS3_FUNC_RESET = 5, /* A PF function reset */
+
/* All PFs under the rootport perform a global reset */
HNS3_GLOBAL_RESET,
HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */
/* All PFs under the rootport perform a global reset */
HNS3_GLOBAL_RESET,
HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */
+ HNS3_NONE_RESET,
HNS3_MAX_RESET
};
HNS3_MAX_RESET
};
@@
-613,6
+628,9
@@
struct hns3_hw {
uint8_t udp_cksum_mode;
struct hns3_port_base_vlan_config port_base_vlan_cfg;
uint8_t udp_cksum_mode;
struct hns3_port_base_vlan_config port_base_vlan_cfg;
+
+ pthread_mutex_t flows_lock; /* rte_flow ops lock */
+
/*
* PMD setup and configuration is not thread safe. Since it is not
* performance sensitive, it is better to guarantee thread-safety
/*
* PMD setup and configuration is not thread safe. Since it is not
* performance sensitive, it is better to guarantee thread-safety
@@
-822,6
+840,8
@@
struct hns3_adapter {
uint32_t rx_func_hint;
uint32_t tx_func_hint;
uint32_t rx_func_hint;
uint32_t tx_func_hint;
+ uint64_t dev_caps_mask;
+
struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned;
};
struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned;
};
@@
-836,6
+856,8
@@
enum {
#define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint"
#define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint"
#define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint"
#define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint"
+#define HNS3_DEVARG_DEV_CAPS_MASK "dev_caps_mask"
+
#define HNS3_DEV_SUPPORT_DCB_B 0x0
#define HNS3_DEV_SUPPORT_COPPER_B 0x1
#define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2
#define HNS3_DEV_SUPPORT_DCB_B 0x0
#define HNS3_DEV_SUPPORT_COPPER_B 0x1
#define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2
@@
-846,6
+868,7
@@
enum {
#define HNS3_DEV_SUPPORT_STASH_B 0x7
#define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9
#define HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B 0xA
#define HNS3_DEV_SUPPORT_STASH_B 0x7
#define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9
#define HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B 0xA
+#define HNS3_DEV_SUPPORT_RAS_IMP_B 0xB
#define hns3_dev_dcb_supported(hw) \
hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
#define hns3_dev_dcb_supported(hw) \
hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
@@
-882,6
+905,9
@@
enum {
#define hns3_dev_outer_udp_cksum_supported(hw) \
hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B)
#define hns3_dev_outer_udp_cksum_supported(hw) \
hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B)
+#define hns3_dev_ras_imp_supported(hw) \
+ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RAS_IMP_B)
+
#define HNS3_DEV_PRIVATE_TO_HW(adapter) \
(&((struct hns3_adapter *)adapter)->hw)
#define HNS3_DEV_PRIVATE_TO_PF(adapter) \
#define HNS3_DEV_PRIVATE_TO_HW(adapter) \
(&((struct hns3_adapter *)adapter)->hw)
#define HNS3_DEV_PRIVATE_TO_PF(adapter) \
@@
-996,15
+1022,9
@@
static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
#define MSEC_PER_SEC 1000L
#define USEC_PER_MSEC 1000L
#define MSEC_PER_SEC 1000L
#define USEC_PER_MSEC 1000L
-static inline uint64_t
-get_timeofday_ms(void)
-{
- struct timeval tv;
-
- (void)gettimeofday(&tv, NULL);
-
- return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC;
-}
+void hns3_clock_gettime(struct timeval *tv);
+uint64_t hns3_clock_calctime_ms(struct timeval *tv);
+uint64_t hns3_clock_gettime_ms(void);
static inline uint64_t
hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr)
static inline uint64_t
hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr)