+static const struct hns3_hw_error ssu_ecc_multi_bit_int_1[] = {
+ {
+ .int_msk = BIT(0),
+ .msg = "ssu_mem32_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = 0,
+ .msg = NULL,
+ .reset_level = HNS3_NONE_RESET
+ }
+};
+
+static const struct hns3_hw_error ssu_common_ecc_int[] = {
+ {
+ .int_msk = BIT(0),
+ .msg = "buf_sum_err",
+ .reset_level = HNS3_NONE_RESET
+ }, {
+ .int_msk = BIT(1),
+ .msg = "ppp_mb_num_err",
+ .reset_level = HNS3_NONE_RESET
+ }, {
+ .int_msk = BIT(2),
+ .msg = "ppp_mbid_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(3),
+ .msg = "ppp_rlt_mac_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(4),
+ .msg = "ppp_rlt_host_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(5),
+ .msg = "cks_edit_position_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(6),
+ .msg = "cks_edit_condition_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(7),
+ .msg = "vlan_edit_condition_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(8),
+ .msg = "vlan_num_ot_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(9),
+ .msg = "vlan_num_in_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = 0,
+ .msg = NULL,
+ .reset_level = HNS3_NONE_RESET
+ }
+};
+
+static const struct hns3_hw_error igu_int[] = {
+ {
+ .int_msk = BIT(0),
+ .msg = "igu_rx_buf0_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(2),
+ .msg = "igu_rx_buf1_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = 0,
+ .msg = NULL,
+ .reset_level = HNS3_NONE_RESET
+ }
+};
+
+static const struct hns3_hw_error msix_ecc_int[] = {
+ {
+ .int_msk = BIT(1),
+ .msg = "msix_nic_ecc_mbit_err",
+ .reset_level = HNS3_NONE_RESET
+ }, {
+ .int_msk = 0,
+ .msg = NULL,
+ .reset_level = HNS3_NONE_RESET
+ }
+};
+
+static const struct hns3_hw_error ppp_mpf_abnormal_int_st1[] = {
+ {
+ .int_msk = BIT(0),
+ .msg = "vf_vlan_ad_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(1),
+ .msg = "umv_mcast_group_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(2),
+ .msg = "umv_key_mem0_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(3),
+ .msg = "umv_key_mem1_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(4),
+ .msg = "umv_key_mem2_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(5),
+ .msg = "umv_key_mem3_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(6),
+ .msg = "umv_ad_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(7),
+ .msg = "rss_tc_mode_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(8),
+ .msg = "rss_idt_mem0_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(9),
+ .msg = "rss_idt_mem1_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(10),
+ .msg = "rss_idt_mem2_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(11),
+ .msg = "rss_idt_mem3_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(12),
+ .msg = "rss_idt_mem4_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(13),
+ .msg = "rss_idt_mem5_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(14),
+ .msg = "rss_idt_mem6_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(15),
+ .msg = "rss_idt_mem7_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(16),
+ .msg = "rss_idt_mem8_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(17),
+ .msg = "rss_idt_mem9_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(18),
+ .msg = "rss_idt_mem10_ecc_m1bit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(19),
+ .msg = "rss_idt_mem11_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(20),
+ .msg = "rss_idt_mem12_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(21),
+ .msg = "rss_idt_mem13_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(22),
+ .msg = "rss_idt_mem14_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(23),
+ .msg = "rss_idt_mem15_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(24),
+ .msg = "port_vlan_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(25),
+ .msg = "mcast_linear_table_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(26),
+ .msg = "mcast_result_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(27),
+ .msg = "flow_director_ad_mem0_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(28),
+ .msg = "flow_director_ad_mem1_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(29),
+ .msg = "rx_vlan_tag_memory_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(30),
+ .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = 0,
+ .msg = NULL,
+ .reset_level = HNS3_NONE_RESET
+ }
+};
+
+static const struct hns3_hw_error ppp_mpf_abnormal_int_st3[] = {
+ {
+ .int_msk = BIT(0),
+ .msg = "hfs_fifo_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(1),
+ .msg = "rslt_descr_fifo_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(2),
+ .msg = "tx_vlan_tag_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(3),
+ .msg = "FD_CN0_memory_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(4),
+ .msg = "FD_CN1_memory_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(5),
+ .msg = "GRO_AD_memory_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = 0,
+ .msg = NULL,
+ .reset_level = HNS3_NONE_RESET
+ }
+};
+
+static const struct hns3_hw_error ppu_mpf_abnormal_int_st3[] = {
+ {
+ .int_msk = BIT(4),
+ .msg = "gro_bd_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(5),
+ .msg = "gro_context_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(6),
+ .msg = "rx_stash_cfg_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(7),
+ .msg = "axi_rd_fbd_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = 0,
+ .msg = NULL,
+ .reset_level = HNS3_NONE_RESET
+ }
+};
+
+static const struct hns3_hw_error tm_sch_int[] = {
+ {
+ .int_msk = BIT(1),
+ .msg = "tm_sch_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(2),
+ .msg = "tm_sch_port_shap_sub_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(3),
+ .msg = "tm_sch_port_shap_sub_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(4),
+ .msg = "tm_sch_pg_pshap_sub_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(5),
+ .msg = "tm_sch_pg_pshap_sub_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(6),
+ .msg = "tm_sch_pg_cshap_sub_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(7),
+ .msg = "tm_sch_pg_cshap_sub_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(8),
+ .msg = "tm_sch_pri_pshap_sub_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(9),
+ .msg = "tm_sch_pri_pshap_sub_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(10),
+ .msg = "tm_sch_pri_cshap_sub_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(11),
+ .msg = "tm_sch_pri_cshap_sub_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(12),
+ .msg = "tm_sch_port_shap_offset_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(13),
+ .msg = "tm_sch_port_shap_offset_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(14),
+ .msg = "tm_sch_pg_pshap_offset_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(15),
+ .msg = "tm_sch_pg_pshap_offset_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(16),
+ .msg = "tm_sch_pg_cshap_offset_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(17),
+ .msg = "tm_sch_pg_cshap_offset_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(18),
+ .msg = "tm_sch_pri_pshap_offset_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(19),
+ .msg = "tm_sch_pri_pshap_offset_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(20),
+ .msg = "tm_sch_pri_cshap_offset_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(21),
+ .msg = "tm_sch_pri_cshap_offset_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(22),
+ .msg = "tm_sch_rq_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(23),
+ .msg = "tm_sch_rq_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(24),
+ .msg = "tm_sch_nq_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(25),
+ .msg = "tm_sch_nq_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(26),
+ .msg = "tm_sch_roce_up_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(27),
+ .msg = "tm_sch_roce_up_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(28),
+ .msg = "tm_sch_rcb_byte_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(29),
+ .msg = "tm_sch_rcb_byte_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(30),
+ .msg = "tm_sch_ssu_byte_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(31),
+ .msg = "tm_sch_ssu_byte_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = 0,
+ .msg = NULL,
+ .reset_level = HNS3_NONE_RESET
+ }
+};
+
+static const struct hns3_hw_error qcn_fifo_int[] = {
+ {
+ .int_msk = BIT(0),
+ .msg = "qcn_shap_gp0_sch_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(1),
+ .msg = "qcn_shap_gp0_sch_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(2),
+ .msg = "qcn_shap_gp1_sch_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(3),
+ .msg = "qcn_shap_gp1_sch_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(4),
+ .msg = "qcn_shap_gp2_sch_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(5),
+ .msg = "qcn_shap_gp2_sch_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(6),
+ .msg = "qcn_shap_gp3_sch_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(7),
+ .msg = "qcn_shap_gp3_sch_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(8),
+ .msg = "qcn_shap_gp0_offset_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(9),
+ .msg = "qcn_shap_gp0_offset_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(10),
+ .msg = "qcn_shap_gp1_offset_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(11),
+ .msg = "qcn_shap_gp1_offset_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(12),
+ .msg = "qcn_shap_gp2_offset_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(13),
+ .msg = "qcn_shap_gp2_offset_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(14),
+ .msg = "qcn_shap_gp3_offset_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(15),
+ .msg = "qcn_shap_gp3_offset_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(16),
+ .msg = "qcn_byte_info_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(17),
+ .msg = "qcn_byte_info_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = 0,
+ .msg = NULL,
+ .reset_level = HNS3_NONE_RESET
+ }
+};
+
+static const struct hns3_hw_error qcn_ecc_int[] = {
+ {
+ .int_msk = BIT(1),
+ .msg = "qcn_byte_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(3),
+ .msg = "qcn_time_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(5),
+ .msg = "qcn_fb_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(7),
+ .msg = "qcn_link_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(9),
+ .msg = "qcn_rate_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(11),
+ .msg = "qcn_tmplt_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(13),
+ .msg = "qcn_shap_cfg_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(15),
+ .msg = "qcn_gp0_barrel_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(17),
+ .msg = "qcn_gp1_barrel_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(19),
+ .msg = "qcn_gp2_barrel_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(21),
+ .msg = "qcn_gp3_barral_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = 0,
+ .msg = NULL,
+ .reset_level = HNS3_NONE_RESET
+ }
+};
+
+static const struct hns3_hw_error ncsi_ecc_int[] = {
+ {
+ .int_msk = BIT(1),
+ .msg = "ncsi_tx_ecc_mbit_err",
+ .reset_level = HNS3_NONE_RESET
+ }, {
+ .int_msk = 0,
+ .msg = NULL,
+ .reset_level = HNS3_NONE_RESET
+ }
+};
+
+static const struct hns3_hw_error ssu_fifo_overflow_int[] = {
+ {
+ .int_msk = BIT(0),
+ .msg = "ig_mac_inf_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(1),
+ .msg = "ig_host_inf_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(2),
+ .msg = "ig_roc_buf_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(3),
+ .msg = "ig_host_data_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(4),
+ .msg = "ig_host_key_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(5),
+ .msg = "tx_qcn_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(6),
+ .msg = "rx_qcn_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(7),
+ .msg = "tx_pf_rd_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(8),
+ .msg = "rx_pf_rd_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(9),
+ .msg = "qm_eof_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(10),
+ .msg = "mb_rlt_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(11),
+ .msg = "dup_uncopy_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(12),
+ .msg = "dup_cnt_rd_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(13),
+ .msg = "dup_cnt_drop_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(14),
+ .msg = "dup_cnt_wrb_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(15),
+ .msg = "host_cmd_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(16),
+ .msg = "mac_cmd_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(17),
+ .msg = "host_cmd_bitmap_empty_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(18),
+ .msg = "mac_cmd_bitmap_empty_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(19),
+ .msg = "dup_bitmap_empty_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(20),
+ .msg = "out_queue_bitmap_empty_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(21),
+ .msg = "bank2_bitmap_empty_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(22),
+ .msg = "bank1_bitmap_empty_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(23),
+ .msg = "bank0_bitmap_empty_int",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = 0,
+ .msg = NULL,
+ .reset_level = HNS3_NONE_RESET
+ }
+};
+
+static const struct hns3_hw_error ssu_ets_tcg_int[] = {
+ {
+ .int_msk = BIT(0),
+ .msg = "ets_rd_int_rx_tcg",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(1),
+ .msg = "ets_wr_int_rx_tcg",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(2),
+ .msg = "ets_rd_int_tx_tcg",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(3),
+ .msg = "ets_wr_int_tx_tcg",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = 0,
+ .msg = NULL,
+ .reset_level = HNS3_NONE_RESET
+ }
+};
+
+static const struct hns3_hw_error igu_egu_tnl_int[] = {
+ {
+ .int_msk = BIT(0),
+ .msg = "rx_buf_overflow",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(1),
+ .msg = "rx_stp_fifo_overflow",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(2),
+ .msg = "rx_stp_fifo_underflow",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(3),
+ .msg = "tx_buf_overflow",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(4),
+ .msg = "tx_buf_underrun",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(5),
+ .msg = "rx_stp_buf_overflow",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = 0,
+ .msg = NULL,
+ .reset_level = HNS3_NONE_RESET
+ }
+};
+
+static const struct hns3_hw_error ssu_port_based_err_int[] = {
+ {
+ .int_msk = BIT(0),
+ .msg = "roc_pkt_without_key_port",
+ .reset_level = HNS3_FUNC_RESET
+ }, {
+ .int_msk = BIT(1),
+ .msg = "tpu_pkt_without_key_port",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(2),
+ .msg = "igu_pkt_without_key_port",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(3),
+ .msg = "roc_eof_mis_match_port",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(4),
+ .msg = "tpu_eof_mis_match_port",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(5),
+ .msg = "igu_eof_mis_match_port",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(6),
+ .msg = "roc_sof_mis_match_port",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(7),
+ .msg = "tpu_sof_mis_match_port",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(8),
+ .msg = "igu_sof_mis_match_port",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(11),
+ .msg = "ets_rd_int_rx_port",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(12),
+ .msg = "ets_wr_int_rx_port",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(13),
+ .msg = "ets_rd_int_tx_port",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = BIT(14),
+ .msg = "ets_wr_int_tx_port",
+ .reset_level = HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = 0,
+ .msg = NULL,
+ .reset_level = HNS3_NONE_RESET
+ }
+};
+
+static const struct hns3_hw_error_desc mpf_ras_err_tbl[] = {
+ {
+ .desc_offset = 0,
+ .data_offset = 0,
+ .msg = "IMP_TCM_ECC_INT_STS",
+ .hw_err = imp_tcm_ecc_int
+ }, {
+ .desc_offset = 0,
+ .data_offset = 1,
+ .msg = "CMDQ_MEM_ECC_INT_STS",
+ .hw_err = cmdq_mem_ecc_int
+ }, {
+ .desc_offset = 0,
+ .data_offset = 2,
+ .msg = "IMP_RD_POISON_INT_STS",
+ .hw_err = imp_rd_poison_int
+ }, {
+ .desc_offset = 0,
+ .data_offset = 3,
+ .msg = "TQP_INT_ECC_INT_STS",
+ .hw_err = tqp_int_ecc_int
+ }, {
+ .desc_offset = 0,
+ .data_offset = 4,
+ .msg = "MSIX_ECC_INT_STS",
+ .hw_err = msix_ecc_int
+ }, {
+ .desc_offset = 2,
+ .data_offset = 2,
+ .msg = "SSU_ECC_MULTI_BIT_INT_0",
+ .hw_err = ssu_ecc_multi_bit_int_0
+ }, {
+ .desc_offset = 2,
+ .data_offset = 3,
+ .msg = "SSU_ECC_MULTI_BIT_INT_1",
+ .hw_err = ssu_ecc_multi_bit_int_1
+ }, {
+ .desc_offset = 2,
+ .data_offset = 4,
+ .msg = "SSU_COMMON_ERR_INT",
+ .hw_err = ssu_common_ecc_int
+ }, {
+ .desc_offset = 3,
+ .data_offset = 0,
+ .msg = "IGU_INT_STS",
+ .hw_err = igu_int
+ }, {
+ .desc_offset = 4,
+ .data_offset = 1,
+ .msg = "PPP_MPF_ABNORMAL_INT_ST1",
+ .hw_err = ppp_mpf_abnormal_int_st1
+ }, {
+ .desc_offset = 4,
+ .data_offset = 3,
+ .msg = "PPP_MPF_ABNORMAL_INT_ST3",
+ .hw_err = ppp_mpf_abnormal_int_st3
+ }, {
+ .desc_offset = 5,
+ .data_offset = 1,
+ .msg = "PPU_MPF_ABNORMAL_INT_ST1",
+ .hw_err = ppu_mpf_abnormal_int_st1
+ }, {
+ .desc_offset = 5,
+ .data_offset = 2,
+ .msg = "PPU_MPF_ABNORMAL_INT_ST2_RAS",
+ .hw_err = ppu_mpf_abnormal_int_st2_ras
+ }, {
+ .desc_offset = 5,
+ .data_offset = 3,
+ .msg = "PPU_MPF_ABNORMAL_INT_ST3",
+ .hw_err = ppu_mpf_abnormal_int_st3
+ }, {
+ .desc_offset = 6,
+ .data_offset = 0,
+ .msg = "TM_SCH_RINT",
+ .hw_err = tm_sch_int
+ }, {
+ .desc_offset = 7,
+ .data_offset = 0,
+ .msg = "QCN_FIFO_RINT",
+ .hw_err = qcn_fifo_int
+ }, {
+ .desc_offset = 7,
+ .data_offset = 1,
+ .msg = "QCN_ECC_RINT",
+ .hw_err = qcn_ecc_int
+ }, {
+ .desc_offset = 9,
+ .data_offset = 0,
+ .msg = "NCSI_ECC_INT_RPT",
+ .hw_err = ncsi_ecc_int
+ }, {
+ .desc_offset = 0,
+ .data_offset = 0,
+ .msg = NULL,
+ .hw_err = NULL
+ }
+};
+
+static const struct hns3_hw_error_desc pf_ras_err_tbl[] = {
+ {
+ .desc_offset = 0,
+ .data_offset = 0,
+ .msg = "SSU_PORT_BASED_ERR_INT_RAS",
+ .hw_err = ssu_port_based_err_int
+ }, {
+ .desc_offset = 0,
+ .data_offset = 1,
+ .msg = "SSU_FIFO_OVERFLOW_INT",
+ .hw_err = ssu_fifo_overflow_int
+ }, {
+ .desc_offset = 0,
+ .data_offset = 2,
+ .msg = "SSU_ETS_TCG_INT",
+ .hw_err = ssu_ets_tcg_int
+ }, {
+ .desc_offset = 1,
+ .data_offset = 0,
+ .msg = "IGU_EGU_TNL_INT_STS",
+ .hw_err = igu_egu_tnl_int
+ }, {
+ .desc_offset = 3,
+ .data_offset = 0,
+ .msg = "PPU_PF_ABNORMAL_INT_ST_RAS",
+ .hw_err = ppu_pf_abnormal_int_ras
+ }, {
+ .desc_offset = 0,
+ .data_offset = 0,
+ .msg = NULL,
+ .hw_err = NULL
+ }
+};
+
+static const struct hns3_hw_error_desc mpf_msix_err_tbl[] = {
+ {
+ .desc_offset = 1,
+ .data_offset = 0,
+ .msg = "MAC_AFIFO_TNL_INT_R",
+ .hw_err = mac_afifo_tnl_int
+ }, {
+ .desc_offset = 5,
+ .data_offset = 2,
+ .msg = "PPU_MPF_ABNORMAL_INT_ST2_MSIX",
+ .hw_err = ppu_mpf_abnormal_int_st2_msix
+ }, {
+ .desc_offset = 0,
+ .data_offset = 0,
+ .msg = NULL,
+ .hw_err = NULL
+ }
+};
+
+static const struct hns3_hw_error_desc pf_msix_err_tbl[] = {
+ {
+ .desc_offset = 0,
+ .data_offset = 0,
+ .msg = "SSU_PORT_BASED_ERR_INT_MSIX",
+ .hw_err = ssu_port_based_pf_int
+ }, {
+ .desc_offset = 2,
+ .data_offset = 0,
+ .msg = "PPP_PF_ABNORMAL_INT_ST0",
+ .hw_err = ppp_pf_abnormal_int
+ }, {
+ .desc_offset = 3,
+ .data_offset = 0,
+ .msg = "PPU_PF_ABNORMAL_INT_ST_MSIX",
+ .hw_err = ppu_pf_abnormal_int_msix
+ }, {
+ .desc_offset = 0,
+ .data_offset = 0,
+ .msg = NULL,
+ .hw_err = NULL
+ }
+};
+
+enum hns3_hw_err_report_type {
+ MPF_MSIX_ERR,
+ PF_MSIX_ERR,
+ MPF_RAS_ERR,
+ PF_RAS_ERR,
+};
+
+static const struct hns3_hw_mod_name hns3_hw_module_name[] = {
+ {
+ .module_name = MODULE_NONE,
+ .msg = "MODULE_NONE"
+ }, {
+ .module_name = MODULE_BIOS_COMMON,
+ .msg = "MODULE_BIOS_COMMON"
+ }, {
+ .module_name = MODULE_GE,
+ .msg = "MODULE_GE"
+ }, {
+ .module_name = MODULE_IGU_EGU,
+ .msg = "MODULE_IGU_EGU"
+ }, {
+ .module_name = MODULE_LGE,
+ .msg = "MODULE_LGE"
+ }, {
+ .module_name = MODULE_NCSI,
+ .msg = "MODULE_NCSI"
+ }, {
+ .module_name = MODULE_PPP,
+ .msg = "MODULE_PPP"
+ }, {
+ .module_name = MODULE_QCN,
+ .msg = "MODULE_QCN"
+ }, {
+ .module_name = MODULE_RCB_RX,
+ .msg = "MODULE_RCB_RX"
+ }, {
+ .module_name = MODULE_RTC,
+ .msg = "MODULE_RTC"
+ }, {
+ .module_name = MODULE_SSU,
+ .msg = "MODULE_SSU"
+ }, {
+ .module_name = MODULE_TM,
+ .msg = "MODULE_TM"
+ }, {
+ .module_name = MODULE_RCB_TX,
+ .msg = "MODULE_RCB_TX"
+ }, {
+ .module_name = MODULE_TXDMA,
+ .msg = "MODULE_TXDMA"
+ }, {
+ .module_name = MODULE_MASTER,
+ .msg = "MODULE_MASTER"
+ }, {
+ .module_name = MODULE_ROH_MAC,
+ .msg = "MODULE_ROH_MAC"
+ }
+};
+
+static const struct hns3_hw_err_type hns3_hw_error_type[] = {
+ {
+ .error_type = NONE_ERROR,
+ .msg = "none_error"
+ }, {
+ .error_type = FIFO_ERROR,
+ .msg = "fifo_error"
+ }, {
+ .error_type = MEMORY_ERROR,
+ .msg = "memory_error"
+ }, {
+ .error_type = POISION_ERROR,
+ .msg = "poision_error"
+ }, {
+ .error_type = MSIX_ECC_ERROR,
+ .msg = "msix_ecc_error"
+ }, {
+ .error_type = TQP_INT_ECC_ERROR,
+ .msg = "tqp_int_ecc_error"
+ }, {
+ .error_type = PF_ABNORMAL_INT_ERROR,
+ .msg = "pf_abnormal_int_error"
+ }, {
+ .error_type = MPF_ABNORMAL_INT_ERROR,
+ .msg = "mpf_abnormal_int_error"
+ }, {
+ .error_type = COMMON_ERROR,
+ .msg = "common_error"
+ }, {
+ .error_type = PORT_ERROR,
+ .msg = "port_error"
+ }, {
+ .error_type = ETS_ERROR,
+ .msg = "ets_error"
+ }, {
+ .error_type = NCSI_ERROR,
+ .msg = "ncsi_error"
+ }, {
+ .error_type = GLB_ERROR,
+ .msg = "glb_error"
+ }
+};
+
+static int
+hns3_config_ncsi_hw_err_int(struct hns3_adapter *hns, bool en)
+{
+ struct hns3_hw *hw = &hns->hw;
+ struct hns3_cmd_desc desc;
+ int ret;
+
+ /* configure NCSI error interrupts */
+ hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_NCSI_INT_EN, false);
+ if (en)
+ desc.data[0] = rte_cpu_to_le_32(HNS3_NCSI_ERR_INT_EN);
+
+ ret = hns3_cmd_send(hw, &desc, 1);
+ if (ret)
+ hns3_err(hw, "fail to %s NCSI error interrupts, ret = %d",
+ en ? "enable" : "disable", ret);
+
+ return ret;
+}
+
+static int
+enable_igu_egu_err_intr(struct hns3_adapter *hns, bool en)
+{
+ struct hns3_hw *hw = &hns->hw;
+ struct hns3_cmd_desc desc;
+ int ret;
+
+ /* configure IGU,EGU error interrupts */
+ hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_IGU_COMMON_INT_EN, false);
+ if (en)
+ desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_ENABLE);
+ else
+ desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_DISABLE);
+
+ desc.data[1] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_EN_MASK);
+
+ ret = hns3_cmd_send(hw, &desc, 1);
+ if (ret) {
+ hns3_err(hw, "fail to %s IGU common interrupts, ret = %d",
+ en ? "enable" : "disable", ret);
+ return ret;
+ }
+
+ hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_IGU_EGU_TNL_INT_EN, false);
+ if (en)
+ desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_TNL_ERR_INT_EN);
+
+ desc.data[1] = rte_cpu_to_le_32(HNS3_IGU_TNL_ERR_INT_EN_MASK);
+
+ ret = hns3_cmd_send(hw, &desc, 1);
+ if (ret) {
+ hns3_err(hw, "fail to %s IGU-EGU TNL interrupts, ret = %d",
+ en ? "enable" : "disable", ret);
+ return ret;
+ }
+
+ return hns3_config_ncsi_hw_err_int(hns, en);
+}
+