+static const struct hns3_hw_error qcn_fifo_int[] = {
+ { .int_msk = BIT(0), .msg = "qcn_shap_gp0_sch_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(1), .msg = "qcn_shap_gp0_sch_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(2), .msg = "qcn_shap_gp1_sch_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(3), .msg = "qcn_shap_gp1_sch_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(4), .msg = "qcn_shap_gp2_sch_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(5), .msg = "qcn_shap_gp2_sch_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(6), .msg = "qcn_shap_gp3_sch_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(7), .msg = "qcn_shap_gp3_sch_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(8), .msg = "qcn_shap_gp0_offset_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(9), .msg = "qcn_shap_gp0_offset_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(10), .msg = "qcn_shap_gp1_offset_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(11), .msg = "qcn_shap_gp1_offset_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(12), .msg = "qcn_shap_gp2_offset_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(13), .msg = "qcn_shap_gp2_offset_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(14), .msg = "qcn_shap_gp3_offset_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(15), .msg = "qcn_shap_gp3_offset_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(16), .msg = "qcn_byte_info_fifo_rd_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(17), .msg = "qcn_byte_info_fifo_wr_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = 0, .msg = NULL,
+ .reset_level = HNS3_NONE_RESET}
+};
+
+static const struct hns3_hw_error qcn_ecc_int[] = {
+ { .int_msk = BIT(1), .msg = "qcn_byte_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(3), .msg = "qcn_time_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(5), .msg = "qcn_fb_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(7), .msg = "qcn_link_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(9), .msg = "qcn_rate_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(11), .msg = "qcn_tmplt_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(13), .msg = "qcn_shap_cfg_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(15), .msg = "qcn_gp0_barrel_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(17), .msg = "qcn_gp1_barrel_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(19), .msg = "qcn_gp2_barrel_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(21), .msg = "qcn_gp3_barral_mem_ecc_mbit_err",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = 0, .msg = NULL,
+ .reset_level = HNS3_NONE_RESET}
+};
+
+static const struct hns3_hw_error ncsi_ecc_int[] = {
+ { .int_msk = BIT(1), .msg = "ncsi_tx_ecc_mbit_err",
+ .reset_level = HNS3_NONE_RESET },
+ { .int_msk = 0, .msg = NULL,
+ .reset_level = HNS3_NONE_RESET}
+};
+
+static const struct hns3_hw_error ssu_fifo_overflow_int[] = {
+ { .int_msk = BIT(0), .msg = "ig_mac_inf_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(1), .msg = "ig_host_inf_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(2), .msg = "ig_roc_buf_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(3), .msg = "ig_host_data_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(4), .msg = "ig_host_key_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(5), .msg = "tx_qcn_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(6), .msg = "rx_qcn_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(7), .msg = "tx_pf_rd_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(8), .msg = "rx_pf_rd_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(9), .msg = "qm_eof_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(10), .msg = "mb_rlt_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(11), .msg = "dup_uncopy_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(12), .msg = "dup_cnt_rd_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(13), .msg = "dup_cnt_drop_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(14), .msg = "dup_cnt_wrb_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(15), .msg = "host_cmd_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(16), .msg = "mac_cmd_fifo_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(17), .msg = "host_cmd_bitmap_empty_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(18), .msg = "mac_cmd_bitmap_empty_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(19), .msg = "dup_bitmap_empty_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(20), .msg = "out_queue_bitmap_empty_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(21), .msg = "bank2_bitmap_empty_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(22), .msg = "bank1_bitmap_empty_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(23), .msg = "bank0_bitmap_empty_int",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = 0, .msg = NULL,
+ .reset_level = HNS3_NONE_RESET}
+};
+
+static const struct hns3_hw_error ssu_ets_tcg_int[] = {
+ { .int_msk = BIT(0), .msg = "ets_rd_int_rx_tcg",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(1), .msg = "ets_wr_int_rx_tcg",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(2), .msg = "ets_rd_int_tx_tcg",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(3), .msg = "ets_wr_int_tx_tcg",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = 0, .msg = NULL,
+ .reset_level = HNS3_NONE_RESET}
+};
+
+static const struct hns3_hw_error igu_egu_tnl_int[] = {
+ { .int_msk = BIT(0), .msg = "rx_buf_overflow",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(1), .msg = "rx_stp_fifo_overflow",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(2), .msg = "rx_stp_fifo_underflow",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(3), .msg = "tx_buf_overflow",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(4), .msg = "tx_buf_underrun",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(5), .msg = "rx_stp_buf_overflow",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = 0, .msg = NULL,
+ .reset_level = HNS3_NONE_RESET}
+};
+
+static const struct hns3_hw_error ssu_port_based_err_int[] = {
+ { .int_msk = BIT(0), .msg = "roc_pkt_without_key_port",
+ .reset_level = HNS3_FUNC_RESET },
+ { .int_msk = BIT(1), .msg = "tpu_pkt_without_key_port",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(2), .msg = "igu_pkt_without_key_port",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(3), .msg = "roc_eof_mis_match_port",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(4), .msg = "tpu_eof_mis_match_port",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(5), .msg = "igu_eof_mis_match_port",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(6), .msg = "roc_sof_mis_match_port",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(7), .msg = "tpu_sof_mis_match_port",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(8), .msg = "igu_sof_mis_match_port",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(11), .msg = "ets_rd_int_rx_port",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(12), .msg = "ets_wr_int_rx_port",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(13), .msg = "ets_rd_int_tx_port",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = BIT(14), .msg = "ets_wr_int_tx_port",
+ .reset_level = HNS3_GLOBAL_RESET },
+ { .int_msk = 0, .msg = NULL,
+ .reset_level = HNS3_NONE_RESET}
+};
+
+static const struct hns3_hw_error_desc mpf_ras_err_tbl[] = {
+ { .desc_offset = 0, .data_offset = 0,
+ .msg = "IMP_TCM_ECC_INT_STS",
+ .hw_err = imp_tcm_ecc_int },
+ { .desc_offset = 0, .data_offset = 1,
+ .msg = "CMDQ_MEM_ECC_INT_STS",
+ .hw_err = cmdq_mem_ecc_int },
+ { .desc_offset = 0, .data_offset = 2,
+ .msg = "IMP_RD_POISON_INT_STS",
+ .hw_err = imp_rd_poison_int },
+ { .desc_offset = 0, .data_offset = 3,
+ .msg = "TQP_INT_ECC_INT_STS",
+ .hw_err = tqp_int_ecc_int },
+ { .desc_offset = 0, .data_offset = 4,
+ .msg = "MSIX_ECC_INT_STS",
+ .hw_err = msix_ecc_int },
+ { .desc_offset = 2, .data_offset = 2,
+ .msg = "SSU_ECC_MULTI_BIT_INT_0",
+ .hw_err = ssu_ecc_multi_bit_int_0 },
+ { .desc_offset = 2, .data_offset = 3,
+ .msg = "SSU_ECC_MULTI_BIT_INT_1",
+ .hw_err = ssu_ecc_multi_bit_int_1 },
+ { .desc_offset = 2, .data_offset = 4,
+ .msg = "SSU_COMMON_ERR_INT",
+ .hw_err = ssu_common_ecc_int },
+ { .desc_offset = 3, .data_offset = 0,
+ .msg = "IGU_INT_STS",
+ .hw_err = igu_int },
+ { .desc_offset = 4, .data_offset = 1,
+ .msg = "PPP_MPF_ABNORMAL_INT_ST1",
+ .hw_err = ppp_mpf_abnormal_int_st1 },
+ { .desc_offset = 4, .data_offset = 3,
+ .msg = "PPP_MPF_ABNORMAL_INT_ST3",
+ .hw_err = ppp_mpf_abnormal_int_st3 },
+ { .desc_offset = 5, .data_offset = 1,
+ .msg = "PPU_MPF_ABNORMAL_INT_ST1",
+ .hw_err = ppu_mpf_abnormal_int_st1 },
+ { .desc_offset = 5, .data_offset = 2,
+ .msg = "PPU_MPF_ABNORMAL_INT_ST2_RAS",
+ .hw_err = ppu_mpf_abnormal_int_st2_ras },
+ { .desc_offset = 5, .data_offset = 3,
+ .msg = "PPU_MPF_ABNORMAL_INT_ST3",
+ .hw_err = ppu_mpf_abnormal_int_st3 },
+ { .desc_offset = 6, .data_offset = 0,
+ .msg = "TM_SCH_RINT",
+ .hw_err = tm_sch_int },
+ { .desc_offset = 7, .data_offset = 0,
+ .msg = "QCN_FIFO_RINT",
+ .hw_err = qcn_fifo_int },
+ { .desc_offset = 7, .data_offset = 1,
+ .msg = "QCN_ECC_RINT",
+ .hw_err = qcn_ecc_int },
+ { .desc_offset = 9, .data_offset = 0,
+ .msg = "NCSI_ECC_INT_RPT",
+ .hw_err = ncsi_ecc_int },
+ { .desc_offset = 0, .data_offset = 0,
+ .msg = NULL,
+ .hw_err = NULL }
+};
+
+static const struct hns3_hw_error_desc pf_ras_err_tbl[] = {
+ { .desc_offset = 0, .data_offset = 0,
+ .msg = "SSU_PORT_BASED_ERR_INT_RAS",
+ .hw_err = ssu_port_based_err_int },
+ { .desc_offset = 0, .data_offset = 1,
+ .msg = "SSU_FIFO_OVERFLOW_INT",
+ .hw_err = ssu_fifo_overflow_int },
+ { .desc_offset = 0, .data_offset = 2,
+ .msg = "SSU_ETS_TCG_INT",
+ .hw_err = ssu_ets_tcg_int },
+ { .desc_offset = 1, .data_offset = 0,
+ .msg = "IGU_EGU_TNL_INT_STS",
+ .hw_err = igu_egu_tnl_int },
+ { .desc_offset = 3, .data_offset = 0,
+ .msg = "PPU_PF_ABNORMAL_INT_ST_RAS",
+ .hw_err = ppu_pf_abnormal_int_ras },
+ { .desc_offset = 0, .data_offset = 0,
+ .msg = NULL,
+ .hw_err = NULL }
+};
+
+static const struct hns3_hw_error_desc mpf_msix_err_tbl[] = {
+ { .desc_offset = 1, .data_offset = 0,
+ .msg = "MAC_AFIFO_TNL_INT_R",
+ .hw_err = mac_afifo_tnl_int },
+ { .desc_offset = 5, .data_offset = 2,
+ .msg = "PPU_MPF_ABNORMAL_INT_ST2_MSIX",
+ .hw_err = ppu_mpf_abnormal_int_st2_msix },
+ { .desc_offset = 0, .data_offset = 0,
+ .msg = NULL,
+ .hw_err = NULL }
+};
+
+static const struct hns3_hw_error_desc pf_msix_err_tbl[] = {
+ { .desc_offset = 0, .data_offset = 0,
+ .msg = "SSU_PORT_BASED_ERR_INT_MSIX",
+ .hw_err = ssu_port_based_pf_int },
+ { .desc_offset = 2, .data_offset = 0,
+ .msg = "PPP_PF_ABNORMAL_INT_ST0",
+ .hw_err = ppp_pf_abnormal_int },
+ { .desc_offset = 3, .data_offset = 0,
+ .msg = "PPU_PF_ABNORMAL_INT_ST_MSIX",
+ .hw_err = ppu_pf_abnormal_int_msix },
+ { .desc_offset = 0, .data_offset = 0,
+ .msg = NULL,
+ .hw_err = NULL }
+};
+
+enum hns3_hw_err_type {
+ MPF_MSIX_ERR,
+ PF_MSIX_ERR,
+ MPF_RAS_ERR,
+ PF_RAS_ERR,
+};
+
+static int
+hns3_config_ncsi_hw_err_int(struct hns3_adapter *hns, bool en)
+{
+ struct hns3_hw *hw = &hns->hw;
+ struct hns3_cmd_desc desc;
+ int ret;
+
+ /* configure NCSI error interrupts */
+ hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_NCSI_INT_EN, false);
+ if (en)
+ desc.data[0] = rte_cpu_to_le_32(HNS3_NCSI_ERR_INT_EN);
+
+ ret = hns3_cmd_send(hw, &desc, 1);
+ if (ret)
+ hns3_err(hw, "fail to %s NCSI error interrupts, ret = %d",
+ en ? "enable" : "disable", ret);
+
+ return ret;
+}
+
+static int
+enable_igu_egu_err_intr(struct hns3_adapter *hns, bool en)
+{
+ struct hns3_hw *hw = &hns->hw;
+ struct hns3_cmd_desc desc;
+ int ret;
+
+ /* configure IGU,EGU error interrupts */
+ hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_IGU_COMMON_INT_EN, false);
+ if (en)
+ desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_ENABLE);
+ else
+ desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_DISABLE);
+
+ desc.data[1] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_EN_MASK);
+
+ ret = hns3_cmd_send(hw, &desc, 1);
+ if (ret) {
+ hns3_err(hw, "fail to %s IGU common interrupts, ret = %d",
+ en ? "enable" : "disable", ret);
+ return ret;
+ }
+
+ hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_IGU_EGU_TNL_INT_EN, false);
+ if (en)
+ desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_TNL_ERR_INT_EN);
+
+ desc.data[1] = rte_cpu_to_le_32(HNS3_IGU_TNL_ERR_INT_EN_MASK);
+
+ ret = hns3_cmd_send(hw, &desc, 1);
+ if (ret) {
+ hns3_err(hw, "fail to %s IGU-EGU TNL interrupts, ret = %d",
+ en ? "enable" : "disable", ret);
+ return ret;
+ }
+
+ return hns3_config_ncsi_hw_err_int(hns, en);
+}
+
+static int
+config_ppp_err_intr(struct hns3_adapter *hns, uint32_t cmd, bool en)
+{
+ struct hns3_hw *hw = &hns->hw;
+ struct hns3_cmd_desc desc[2];
+ int ret;
+
+ /* configure PPP error interrupts */
+ hns3_cmd_setup_basic_desc(&desc[0], cmd, false);
+ desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
+ hns3_cmd_setup_basic_desc(&desc[1], cmd, false);
+
+ if (cmd == HNS3_OPC_PPP_CMD0_INT_CMD) {
+ if (en) {
+ desc[0].data[0] =
+ rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN);
+ desc[0].data[1] =
+ rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN);
+ desc[0].data[4] =
+ rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN);
+ }
+
+ desc[1].data[0] =
+ rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN_MASK);
+ desc[1].data[1] =
+ rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN_MASK);
+ desc[1].data[2] =
+ rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN_MASK);
+ } else if (cmd == HNS3_OPC_PPP_CMD1_INT_CMD) {
+ if (en) {
+ desc[0].data[0] =
+ rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN);
+ desc[0].data[1] =
+ rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN);
+ }
+
+ desc[1].data[0] =
+ rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN_MASK);
+ desc[1].data[1] =
+ rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN_MASK);
+ }
+
+ ret = hns3_cmd_send(hw, &desc[0], 2);
+ if (ret)
+ hns3_err(hw, "fail to %s PPP error int, ret = %d",
+ en ? "enable" : "disable", ret);
+
+ return ret;
+}
+
+static int
+enable_ppp_err_intr(struct hns3_adapter *hns, bool en)
+{
+ int ret;
+
+ ret = config_ppp_err_intr(hns, HNS3_OPC_PPP_CMD0_INT_CMD, en);
+ if (ret)
+ return ret;
+
+ return config_ppp_err_intr(hns, HNS3_OPC_PPP_CMD1_INT_CMD, en);
+}
+
+static int
+enable_ssu_err_intr(struct hns3_adapter *hns, bool en)
+{
+ struct hns3_hw *hw = &hns->hw;
+ struct hns3_cmd_desc desc[2];
+ int ret;
+
+ /* configure SSU ecc error interrupts */
+ hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_SSU_ECC_INT_CMD, false);
+ desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
+ hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_SSU_ECC_INT_CMD, false);
+ if (en) {
+ desc[0].data[0] =
+ rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN);
+ desc[0].data[1] =
+ rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN);
+ desc[0].data[4] =
+ rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN);
+ }
+
+ desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK);
+ desc[1].data[1] =
+ rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK);
+ desc[1].data[2] = rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN_MASK);
+
+ ret = hns3_cmd_send(hw, &desc[0], 2);
+ if (ret) {
+ hns3_err(hw, "fail to %s SSU ECC error interrupt, ret = %d",
+ en ? "enable" : "disable", ret);
+ return ret;
+ }
+
+ /* configure SSU common error interrupts */
+ hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_SSU_COMMON_INT_CMD, false);
+ desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
+ hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_SSU_COMMON_INT_CMD, false);
+
+ if (en) {
+ desc[0].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN);