/* bar registers for tqp interrupt */
#define HNS3_TQP_INTR_CTRL_REG 0x20000
#define HNS3_TQP_INTR_GL0_REG 0x20100
#define HNS3_TQP_INTR_GL1_REG 0x20200
#define HNS3_TQP_INTR_GL2_REG 0x20300
#define HNS3_TQP_INTR_RL_REG 0x20900
/* bar registers for tqp interrupt */
#define HNS3_TQP_INTR_CTRL_REG 0x20000
#define HNS3_TQP_INTR_GL0_REG 0x20100
#define HNS3_TQP_INTR_GL1_REG 0x20200
#define HNS3_TQP_INTR_GL2_REG 0x20300
#define HNS3_TQP_INTR_RL_REG 0x20900