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net/vmxnet3: support MSI-X interrupt
[dpdk.git]
/
drivers
/
net
/
i40e
/
i40e_ethdev.c
diff --git
a/drivers/net/i40e/i40e_ethdev.c
b/drivers/net/i40e/i40e_ethdev.c
index
2076717
..
7b230e2
100644
(file)
--- a/
drivers/net/i40e/i40e_ethdev.c
+++ b/
drivers/net/i40e/i40e_ethdev.c
@@
-27,6
+27,7
@@
#include <rte_tailq.h>
#include <rte_hash_crc.h>
#include <rte_bitmap.h>
#include <rte_tailq.h>
#include <rte_hash_crc.h>
#include <rte_bitmap.h>
+#include <rte_os_shim.h>
#include "i40e_logs.h"
#include "base/i40e_prototype.h"
#include "i40e_logs.h"
#include "base/i40e_prototype.h"
@@
-731,10
+732,11
@@
i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
uint32_t reg_val)
{
uint32_t ori_reg_val;
uint32_t reg_val)
{
uint32_t ori_reg_val;
- struct rte_eth_dev *dev;
+ struct rte_eth_dev_data *dev_data =
+ ((struct i40e_adapter *)hw->back)->pf.dev_data;
+ struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
- dev = ((struct i40e_adapter *)hw->back)->eth_dev;
i40e_write_rx_ctl(hw, reg_addr, reg_val);
if (ori_reg_val != reg_val)
PMD_DRV_LOG(WARNING,
i40e_write_rx_ctl(hw, reg_addr, reg_val);
if (ori_reg_val != reg_val)
PMD_DRV_LOG(WARNING,
@@
-853,6
+855,8
@@
floating_veb_list_handler(__rte_unused const char *key,
idx = strtoul(floating_veb_value, &end, 10);
if (errno || end == NULL)
return -1;
idx = strtoul(floating_veb_value, &end, 10);
if (errno || end == NULL)
return -1;
+ if (idx < 0)
+ return -1;
while (isblank(*end))
end++;
if (*end == '-') {
while (isblank(*end))
end++;
if (*end == '-') {
@@
-1084,6
+1088,7
@@
i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
char fdir_hash_name[RTE_HASH_NAMESIZE];
uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
uint32_t best = hw->func_caps.fd_filters_best_effort;
char fdir_hash_name[RTE_HASH_NAMESIZE];
uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
uint32_t best = hw->func_caps.fd_filters_best_effort;
+ enum i40e_filter_pctype pctype;
struct rte_bitmap *bmp = NULL;
uint32_t bmp_size;
void *mem = NULL;
struct rte_bitmap *bmp = NULL;
uint32_t bmp_size;
void *mem = NULL;
@@
-1132,6
+1137,10
@@
i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
goto err_fdir_filter_array_alloc;
}
goto err_fdir_filter_array_alloc;
}
+ for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
+ pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
+ pf->fdir.flow_count[pctype] = 0;
+
fdir_info->fdir_space_size = alloc + best;
fdir_info->fdir_actual_cnt = 0;
fdir_info->fdir_guarantee_total_space = alloc;
fdir_info->fdir_space_size = alloc + best;
fdir_info->fdir_actual_cnt = 0;
fdir_info->fdir_guarantee_total_space = alloc;
@@
-1318,7
+1327,9
@@
i40e_aq_debug_write_global_register(struct i40e_hw *hw,
struct i40e_asq_cmd_details *cmd_details)
{
uint64_t ori_reg_val;
struct i40e_asq_cmd_details *cmd_details)
{
uint64_t ori_reg_val;
- struct rte_eth_dev *dev;
+ struct rte_eth_dev_data *dev_data =
+ ((struct i40e_adapter *)hw->back)->pf.dev_data;
+ struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
int ret;
ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
int ret;
ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
@@
-1328,7
+1339,6
@@
i40e_aq_debug_write_global_register(struct i40e_hw *hw,
reg_addr);
return -EIO;
}
reg_addr);
return -EIO;
}
- dev = ((struct i40e_adapter *)hw->back)->eth_dev;
if (ori_reg_val != reg_val)
PMD_DRV_LOG(WARNING,
if (ori_reg_val != reg_val)
PMD_DRV_LOG(WARNING,
@@
-1447,7
+1457,6
@@
eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
- pf->adapter->eth_dev = dev;
pf->dev_data = dev->data;
hw->back = I40E_PF_TO_ADAPTER(pf);
pf->dev_data = dev->data;
hw->back = I40E_PF_TO_ADAPTER(pf);
@@
-1974,7
+1983,7
@@
err:
void
i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
{
void
i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
{
- struct rte_eth_dev *dev =
vsi->adapter->eth_dev
;
+ struct rte_eth_dev *dev =
I40E_VSI_TO_ETH_DEV(vsi)
;
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
@@
-2090,7
+2099,7
@@
__vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
int
i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
{
int
i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
{
- struct rte_eth_dev *dev =
vsi->adapter->eth_dev
;
+ struct rte_eth_dev *dev =
I40E_VSI_TO_ETH_DEV(vsi)
;
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
@@
-2166,7
+2175,7
@@
i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
void
i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
{
void
i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
{
- struct rte_eth_dev *dev =
vsi->adapter->eth_dev
;
+ struct rte_eth_dev *dev =
I40E_VSI_TO_ETH_DEV(vsi)
;
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
@@
-2193,7
+2202,7
@@
i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
void
i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
{
void
i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
{
- struct rte_eth_dev *dev =
vsi->adapter->eth_dev
;
+ struct rte_eth_dev *dev =
I40E_VSI_TO_ETH_DEV(vsi)
;
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
@@
-2306,7
+2315,8
@@
i40e_phy_conf_link(struct i40e_hw *hw,
phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
- I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
+ I40E_AQ_PHY_TYPE_EXT_25G_LR | I40E_AQ_PHY_TYPE_EXT_25G_AOC |
+ I40E_AQ_PHY_TYPE_EXT_25G_ACC) : 0;
phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
phy_conf.eee_capability = phy_ab.eee_capability;
phy_conf.eeer = phy_ab.eeer_val;
phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
phy_conf.eee_capability = phy_ab.eee_capability;
phy_conf.eeer = phy_ab.eeer_val;
@@
-3685,9
+3695,11
@@
i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
((hw->nvm.version >> 4) & 0xff),
(hw->nvm.version & 0xf), hw->nvm.eetrack,
ver, build, patch);
((hw->nvm.version >> 4) & 0xff),
(hw->nvm.version & 0xf), hw->nvm.eetrack,
ver, build, patch);
+ if (ret < 0)
+ return -EINVAL;
ret += 1; /* add the size of '\0' */
ret += 1; /* add the size of '\0' */
- if (fw_size < (
u32
)ret)
+ if (fw_size < (
size_t
)ret)
return ret;
else
return 0;
return ret;
else
return 0;
@@
-4542,13
+4554,15
@@
i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
u64 size,
u32 alignment)
{
u64 size,
u32 alignment)
{
+ static uint64_t i40e_dma_memzone_id;
const struct rte_memzone *mz = NULL;
char z_name[RTE_MEMZONE_NAMESIZE];
if (!mem)
return I40E_ERR_PARAM;
const struct rte_memzone *mz = NULL;
char z_name[RTE_MEMZONE_NAMESIZE];
if (!mem)
return I40E_ERR_PARAM;
- snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
+ snprintf(z_name, sizeof(z_name), "i40e_dma_%" PRIu64,
+ __atomic_fetch_add(&i40e_dma_memzone_id, 1, __ATOMIC_RELAXED));
mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
if (!mz)
mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
if (!mz)
@@
-6405,8
+6419,7
@@
i40e_dev_tx_init(struct i40e_pf *pf)
break;
}
if (ret == I40E_SUCCESS)
break;
}
if (ret == I40E_SUCCESS)
- i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
- ->eth_dev);
+ i40e_set_tx_function(&rte_eth_devices[pf->dev_data->port_id]);
return ret;
}
return ret;
}
@@
-6434,8
+6447,7
@@
i40e_dev_rx_init(struct i40e_pf *pf)
}
}
if (ret == I40E_SUCCESS)
}
}
if (ret == I40E_SUCCESS)
- i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
- ->eth_dev);
+ i40e_set_rx_function(&rte_eth_devices[pf->dev_data->port_id]);
return ret;
}
return ret;
}
@@
-7874,7
+7886,7
@@
i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
- struct rte_eth_dev *dev =
((struct i40e_adapter *)hw->back)->eth_dev
;
+ struct rte_eth_dev *dev =
&rte_eth_devices[pf->dev_data->port_id]
;
enum i40e_status_code status = I40E_SUCCESS;
if (pf->support_multi_driver) {
enum i40e_status_code status = I40E_SUCCESS;
if (pf->support_multi_driver) {
@@
-7935,7
+7947,7
@@
i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
- struct rte_eth_dev *dev =
((struct i40e_adapter *)hw->back)->eth_dev
;
+ struct rte_eth_dev *dev =
&rte_eth_devices[pf->dev_data->port_id]
;
enum i40e_status_code status = I40E_SUCCESS;
if (pf->support_multi_driver) {
enum i40e_status_code status = I40E_SUCCESS;
if (pf->support_multi_driver) {
@@
-8010,7
+8022,7
@@
i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
- struct rte_eth_dev *dev =
((struct i40e_adapter *)hw->back)->eth_dev
;
+ struct rte_eth_dev *dev =
&rte_eth_devices[pf->dev_data->port_id]
;
enum i40e_status_code status = I40E_SUCCESS;
if (pf->support_multi_driver) {
enum i40e_status_code status = I40E_SUCCESS;
if (pf->support_multi_driver) {
@@
-8098,7
+8110,7
@@
i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
- struct rte_eth_dev *dev =
((struct i40e_adapter *)hw->back)->eth_dev
;
+ struct rte_eth_dev *dev =
&rte_eth_devices[pf->dev_data->port_id]
;
enum i40e_status_code status = I40E_SUCCESS;
if (pf->support_multi_driver) {
enum i40e_status_code status = I40E_SUCCESS;
if (pf->support_multi_driver) {
@@
-8173,7
+8185,7
@@
i40e_replace_port_l1_filter(struct i40e_pf *pf,
struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
enum i40e_status_code status = I40E_SUCCESS;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
enum i40e_status_code status = I40E_SUCCESS;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
- struct rte_eth_dev *dev =
((struct i40e_adapter *)hw->back)->eth_dev
;
+ struct rte_eth_dev *dev =
&rte_eth_devices[pf->dev_data->port_id]
;
if (pf->support_multi_driver) {
PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
if (pf->support_multi_driver) {
PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
@@
-8245,7
+8257,7
@@
i40e_replace_port_cloud_filter(struct i40e_pf *pf,
struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
enum i40e_status_code status = I40E_SUCCESS;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
enum i40e_status_code status = I40E_SUCCESS;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
- struct rte_eth_dev *dev =
((struct i40e_adapter *)hw->back)->eth_dev
;
+ struct rte_eth_dev *dev =
&rte_eth_devices[pf->dev_data->port_id]
;
if (pf->support_multi_driver) {
PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
if (pf->support_multi_driver) {
PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
@@
-9572,9
+9584,10
@@
void
i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
{
uint32_t reg = i40e_read_rx_ctl(hw, addr);
i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
{
uint32_t reg = i40e_read_rx_ctl(hw, addr);
- struct rte_eth_dev *dev;
+ struct rte_eth_dev_data *dev_data =
+ ((struct i40e_adapter *)hw->back)->pf.dev_data;
+ struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
- dev = ((struct i40e_adapter *)hw->back)->eth_dev;
if (reg != val) {
i40e_write_rx_ctl(hw, addr, val);
PMD_DRV_LOG(WARNING,
if (reg != val) {
i40e_write_rx_ctl(hw, addr, val);
PMD_DRV_LOG(WARNING,
@@
-11659,9
+11672,6
@@
static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
uint32_t value = 0;
uint32_t i;
uint32_t value = 0;
uint32_t i;
- if (!info || !info->length || !info->data)
- return -EINVAL;
-
if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
is_sfp = true;
if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
is_sfp = true;
@@
-12369,7
+12379,7
@@
i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
- struct rte_eth_dev *dev =
((struct i40e_adapter *)hw->back)->eth_dev
;
+ struct rte_eth_dev *dev =
&rte_eth_devices[pf->dev_data->port_id]
;
if (pf->support_multi_driver) {
PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
if (pf->support_multi_driver) {
PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
@@
-12446,13
+12456,13
@@
i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
return ret;
}
return ret;
}
-RTE_LOG_REGISTER
(i40e_logtype_init, pmd.net.i40e.
init, NOTICE);
-RTE_LOG_REGISTER
(i40e_logtype_driver, pmd.net.i40e.
driver, NOTICE);
+RTE_LOG_REGISTER
_SUFFIX(i40e_logtype_init,
init, NOTICE);
+RTE_LOG_REGISTER
_SUFFIX(i40e_logtype_driver,
driver, NOTICE);
#ifdef RTE_ETHDEV_DEBUG_RX
#ifdef RTE_ETHDEV_DEBUG_RX
-RTE_LOG_REGISTER
(i40e_logtype_rx, pmd.net.i40e.
rx, DEBUG);
+RTE_LOG_REGISTER
_SUFFIX(i40e_logtype_rx,
rx, DEBUG);
#endif
#ifdef RTE_ETHDEV_DEBUG_TX
#endif
#ifdef RTE_ETHDEV_DEBUG_TX
-RTE_LOG_REGISTER
(i40e_logtype_tx, pmd.net.i40e.
tx, DEBUG);
+RTE_LOG_REGISTER
_SUFFIX(i40e_logtype_tx,
tx, DEBUG);
#endif
RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
#endif
RTE_PMD_REGISTER_PARAM_STRING(net_i40e,