- } else {
- ret = 0;
- }
- PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
- I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
-
- return ret;
-}
-
-static int
-i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
-{
- int ret = -EINVAL;
-
- if (!hw || !cfg)
- return -EINVAL;
-
- switch (cfg->cfg_type) {
- case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
- ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
- break;
- default:
- PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
- break;
- }
-
- return ret;
-}
-
-static int
-i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
- enum rte_filter_op filter_op,
- void *arg)
-{
- struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- int ret = I40E_ERR_PARAM;
-
- switch (filter_op) {
- case RTE_ETH_FILTER_SET:
- ret = i40e_dev_global_config_set(hw,
- (struct rte_eth_global_cfg *)arg);
- break;
- default:
- PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
- break;
- }
-
- return ret;
-}
-
-static int
-i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
- enum rte_filter_op filter_op,
- void *arg)
-{
- struct rte_eth_tunnel_filter_conf *filter;
- struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
- int ret = I40E_SUCCESS;
-
- filter = (struct rte_eth_tunnel_filter_conf *)(arg);
-
- if (i40e_tunnel_filter_param_check(pf, filter) < 0)
- return I40E_ERR_PARAM;
-
- switch (filter_op) {
- case RTE_ETH_FILTER_NOP:
- if (!(pf->flags & I40E_FLAG_VXLAN))
- ret = I40E_NOT_SUPPORTED;
- break;
- case RTE_ETH_FILTER_ADD:
- ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
- break;
- case RTE_ETH_FILTER_DELETE:
- ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
- break;
- default:
- PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
- ret = I40E_ERR_PARAM;
- break;
- }
-
- return ret;
-}
-
-static int
-i40e_pf_config_mq_rx(struct i40e_pf *pf)
-{
- int ret = 0;
- enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
-
- /* RSS setup */
- if (mq_mode & ETH_MQ_RX_RSS_FLAG)
- ret = i40e_pf_config_rss(pf);
- else
- i40e_pf_disable_rss(pf);
-
- return ret;
-}
-
-/* Get the symmetric hash enable configurations per port */
-static void
-i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
-{
- uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
-
- *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
-}
-
-/* Set the symmetric hash enable configurations per port */
-static void
-i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
-{
- uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
-
- if (enable > 0) {
- if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
- PMD_DRV_LOG(INFO,
- "Symmetric hash has already been enabled");
- return;
- }
- reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
- } else {
- if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
- PMD_DRV_LOG(INFO,
- "Symmetric hash has already been disabled");
- return;
- }
- reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
- }
- i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
- I40E_WRITE_FLUSH(hw);
-}
-
-/*
- * Get global configurations of hash function type and symmetric hash enable
- * per flow type (pctype). Note that global configuration means it affects all
- * the ports on the same NIC.
- */
-static int
-i40e_get_hash_filter_global_config(struct i40e_hw *hw,
- struct rte_eth_hash_global_conf *g_cfg)
-{
- struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
- uint32_t reg;
- uint16_t i, j;
-
- memset(g_cfg, 0, sizeof(*g_cfg));
- reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
- if (reg & I40E_GLQF_CTL_HTOEP_MASK)
- g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
- else
- g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
- PMD_DRV_LOG(DEBUG, "Hash function is %s",
- (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
-
- /*
- * As i40e supports less than 64 flow types, only first 64 bits need to
- * be checked.
- */
- for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
- g_cfg->valid_bit_mask[i] = 0ULL;
- g_cfg->sym_hash_enable_mask[i] = 0ULL;
- }
-
- g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
-
- for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
- if (!adapter->pctypes_tbl[i])
- continue;
- for (j = I40E_FILTER_PCTYPE_INVALID + 1;
- j < I40E_FILTER_PCTYPE_MAX; j++) {
- if (adapter->pctypes_tbl[i] & (1ULL << j)) {
- reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
- if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
- g_cfg->sym_hash_enable_mask[0] |=
- (1ULL << i);
- }
- }
- }
- }
-
- return 0;
-}
-
-static int
-i40e_hash_global_config_check(const struct i40e_adapter *adapter,
- const struct rte_eth_hash_global_conf *g_cfg)
-{
- uint32_t i;
- uint64_t mask0, i40e_mask = adapter->flow_types_mask;
-
- if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
- g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
- g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
- PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
- g_cfg->hash_func);
- return -EINVAL;
- }
-
- /*
- * As i40e supports less than 64 flow types, only first 64 bits need to
- * be checked.
- */
- mask0 = g_cfg->valid_bit_mask[0];
- for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
- if (i == 0) {
- /* Check if any unsupported flow type configured */
- if ((mask0 | i40e_mask) ^ i40e_mask)
- goto mask_err;
- } else {
- if (g_cfg->valid_bit_mask[i])
- goto mask_err;
- }
- }
-
- return 0;
-
-mask_err:
- PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
-
- return -EINVAL;
-}
-
-/*
- * Set global configurations of hash function type and symmetric hash enable
- * per flow type (pctype). Note any modifying global configuration will affect
- * all the ports on the same NIC.
- */
-static int
-i40e_set_hash_filter_global_config(struct i40e_hw *hw,
- struct rte_eth_hash_global_conf *g_cfg)
-{
- struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
- struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
- int ret;
- uint16_t i, j;
- uint32_t reg;
- uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
-
- if (pf->support_multi_driver) {
- PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
- return -ENOTSUP;
- }
-
- /* Check the input parameters */
- ret = i40e_hash_global_config_check(adapter, g_cfg);
- if (ret < 0)
- return ret;
-
- /*
- * As i40e supports less than 64 flow types, only first 64 bits need to
- * be configured.
- */
- for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
- if (mask0 & (1UL << i)) {
- reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
- I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
-
- for (j = I40E_FILTER_PCTYPE_INVALID + 1;
- j < I40E_FILTER_PCTYPE_MAX; j++) {
- if (adapter->pctypes_tbl[i] & (1ULL << j))
- i40e_write_global_rx_ctl(hw,
- I40E_GLQF_HSYM(j),
- reg);
- }
- }