+void
+i40e_notify_vf_link_status(struct rte_eth_dev *dev, struct i40e_pf_vf *vf)
+{
+ struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
+ struct virtchnl_pf_event event;
+ uint16_t vf_id = vf->vf_idx;
+ uint32_t tval, rval;
+
+ event.event = VIRTCHNL_EVENT_LINK_CHANGE;
+ event.event_data.link_event.link_status =
+ dev->data->dev_link.link_status;
+
+ /* need to convert the ETH_SPEED_xxx into VIRTCHNL_LINK_SPEED_xxx */
+ switch (dev->data->dev_link.link_speed) {
+ case ETH_SPEED_NUM_100M:
+ event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_100MB;
+ break;
+ case ETH_SPEED_NUM_1G:
+ event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_1GB;
+ break;
+ case ETH_SPEED_NUM_10G:
+ event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_10GB;
+ break;
+ case ETH_SPEED_NUM_20G:
+ event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_20GB;
+ break;
+ case ETH_SPEED_NUM_25G:
+ event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_25GB;
+ break;
+ case ETH_SPEED_NUM_40G:
+ event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_40GB;
+ break;
+ default:
+ event.event_data.link_event.link_speed =
+ VIRTCHNL_LINK_SPEED_UNKNOWN;
+ break;
+ }
+
+ tval = I40E_READ_REG(hw, I40E_VF_ATQLEN(vf_id));
+ rval = I40E_READ_REG(hw, I40E_VF_ARQLEN(vf_id));
+
+ if (tval & I40E_VF_ATQLEN_ATQLEN_MASK ||
+ tval & I40E_VF_ATQLEN_ATQENABLE_MASK ||
+ rval & I40E_VF_ARQLEN_ARQLEN_MASK ||
+ rval & I40E_VF_ARQLEN_ARQENABLE_MASK)
+ i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_EVENT,
+ I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
+}
+
+/**
+ * i40e_vc_notify_vf_reset
+ * @vf: pointer to the VF structure
+ *
+ * indicate a pending reset to the given VF
+ **/
+static void
+i40e_vc_notify_vf_reset(struct i40e_pf_vf *vf)
+{
+ struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
+ struct virtchnl_pf_event pfe;
+ int abs_vf_id;
+ uint16_t vf_id = vf->vf_idx;
+
+ abs_vf_id = vf_id + hw->func_caps.vf_base_id;
+ pfe.event = VIRTCHNL_EVENT_RESET_IMPENDING;
+ pfe.severity = PF_EVENT_SEVERITY_CERTAIN_DOOM;
+ i40e_aq_send_msg_to_vf(hw, abs_vf_id, VIRTCHNL_OP_EVENT, 0, (u8 *)&pfe,
+ sizeof(struct virtchnl_pf_event), NULL);
+}
+
+static int
+i40e_pf_host_process_cmd_request_queues(struct i40e_pf_vf *vf, uint8_t *msg)
+{
+ struct virtchnl_vf_res_request *vfres =
+ (struct virtchnl_vf_res_request *)msg;
+ struct i40e_pf *pf;
+ uint32_t req_pairs = vfres->num_queue_pairs;
+ uint32_t cur_pairs = vf->vsi->nb_used_qps;
+
+ pf = vf->pf;
+
+ if (!rte_is_power_of_2(req_pairs))
+ req_pairs = i40e_align_floor(req_pairs) << 1;
+
+ if (req_pairs == 0) {
+ PMD_DRV_LOG(ERR, "VF %d tried to request 0 queues. Ignoring.\n",
+ vf->vf_idx);
+ } else if (req_pairs > I40E_MAX_QP_NUM_PER_VF) {
+ PMD_DRV_LOG(ERR,
+ "VF %d tried to request more than %d queues.\n",
+ vf->vf_idx,
+ I40E_MAX_QP_NUM_PER_VF);
+ vfres->num_queue_pairs = I40E_MAX_QP_NUM_PER_VF;
+ } else if (req_pairs > cur_pairs + pf->qp_pool.num_free) {
+ PMD_DRV_LOG(ERR, "VF %d requested %d queues (rounded to %d) "
+ "but only %d available\n",
+ vf->vf_idx,
+ vfres->num_queue_pairs,
+ req_pairs,
+ cur_pairs + pf->qp_pool.num_free);
+ vfres->num_queue_pairs = i40e_align_floor(pf->qp_pool.num_free +
+ cur_pairs);
+ } else {
+ i40e_vc_notify_vf_reset(vf);
+ vf->vsi->nb_qps = req_pairs;
+ pf->vf_nb_qps = req_pairs;
+ i40e_pf_host_process_cmd_reset_vf(vf);
+
+ return 0;
+ }
+
+ return i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_REQUEST_QUEUES, 0,
+ (u8 *)vfres, sizeof(*vfres));
+}
+
+static void
+i40e_pf_host_process_cmd_get_rss_hena(struct i40e_pf_vf *vf)
+{
+ struct virtchnl_rss_hena vrh = {0};
+ struct i40e_pf *pf = vf->pf;
+
+ if (pf->adapter->hw.mac.type == I40E_MAC_X722)
+ vrh.hena = I40E_DEFAULT_RSS_HENA_EXPANDED;
+ else
+ vrh.hena = I40E_DEFAULT_RSS_HENA;
+
+ i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_GET_RSS_HENA_CAPS,
+ I40E_SUCCESS, (uint8_t *)&vrh, sizeof(vrh));
+}
+
+static void
+i40e_pf_host_process_cmd_set_rss_hena(struct i40e_pf_vf *vf, uint8_t *msg)
+{
+ struct virtchnl_rss_hena *vrh =
+ (struct virtchnl_rss_hena *)msg;
+ struct i40e_hw *hw = &vf->pf->adapter->hw;
+
+ i40e_write_rx_ctl(hw, I40E_VFQF_HENA1(0, vf->vf_idx),
+ (uint32_t)vrh->hena);
+ i40e_write_rx_ctl(hw, I40E_VFQF_HENA1(1, vf->vf_idx),
+ (uint32_t)(vrh->hena >> 32));
+
+ i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_SET_RSS_HENA,
+ I40E_SUCCESS, NULL, 0);
+}
+