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net/sfc/base: remove unused defined for WPTR alignment
[dpdk.git]
/
drivers
/
net
/
i40e
/
i40e_rxtx_vec_neon.c
diff --git
a/drivers/net/i40e/i40e_rxtx_vec_neon.c
b/drivers/net/i40e/i40e_rxtx_vec_neon.c
index
ca6b1f4
..
b5685e2
100644
(file)
--- a/
drivers/net/i40e/i40e_rxtx_vec_neon.c
+++ b/
drivers/net/i40e/i40e_rxtx_vec_neon.c
@@
-81,13
+81,13
@@
i40e_rxq_rearm(struct i40e_rx_queue *rxq)
mb0 = rxep[0].mbuf;
mb1 = rxep[1].mbuf;
mb0 = rxep[0].mbuf;
mb1 = rxep[1].mbuf;
- paddr = mb0->buf_
physaddr
+ RTE_PKTMBUF_HEADROOM;
+ paddr = mb0->buf_
iova
+ RTE_PKTMBUF_HEADROOM;
dma_addr0 = vdupq_n_u64(paddr);
/* flush desc with pa dma_addr */
vst1q_u64((uint64_t *)&rxdp++->read, dma_addr0);
dma_addr0 = vdupq_n_u64(paddr);
/* flush desc with pa dma_addr */
vst1q_u64((uint64_t *)&rxdp++->read, dma_addr0);
- paddr = mb1->buf_
physaddr
+ RTE_PKTMBUF_HEADROOM;
+ paddr = mb1->buf_
iova
+ RTE_PKTMBUF_HEADROOM;
dma_addr1 = vdupq_n_u64(paddr);
vst1q_u64((uint64_t *)&rxdp++->read, dma_addr1);
}
dma_addr1 = vdupq_n_u64(paddr);
vst1q_u64((uint64_t *)&rxdp++->read, dma_addr1);
}
@@
-137,7
+137,7
@@
desc_to_olflags_v(struct i40e_rx_queue *rxq, uint64x2_t descs[4],
/* map rss and vlan type to rss hash and vlan flag */
const uint8x16_t vlan_flags = {
0, 0, 0, 0,
/* map rss and vlan type to rss hash and vlan flag */
const uint8x16_t vlan_flags = {
0, 0, 0, 0,
- PKT_RX_VLAN
_PKT
| PKT_RX_VLAN_STRIPPED, 0, 0, 0,
+ PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0};
0, 0, 0, 0,
0, 0, 0, 0};
@@
-197,11
+197,11
@@
desc_to_olflags_v(struct i40e_rx_queue *rxq, uint64x2_t descs[4],
}
#define PKTLEN_SHIFT 10
}
#define PKTLEN_SHIFT 10
-
-#define I40E_VPMD_DESC_DD_MASK 0x0001000100010001ULL
+#define I40E_UINT16_BIT (CHAR_BIT * sizeof(uint16_t))
static inline void
static inline void
-desc_to_ptype_v(uint64x2_t descs[4], struct rte_mbuf **rx_pkts)
+desc_to_ptype_v(uint64x2_t descs[4], struct rte_mbuf **rx_pkts,
+ uint32_t *ptype_tbl)
{
int i;
uint8_t ptype;
{
int i;
uint8_t ptype;
@@
-210,7
+210,7
@@
desc_to_ptype_v(uint64x2_t descs[4], struct rte_mbuf **rx_pkts)
for (i = 0; i < 4; i++) {
tmp = vreinterpretq_u8_u64(vshrq_n_u64(descs[i], 30));
ptype = vgetq_lane_u8(tmp, 8);
for (i = 0; i < 4; i++) {
tmp = vreinterpretq_u8_u64(vshrq_n_u64(descs[i], 30));
ptype = vgetq_lane_u8(tmp, 8);
- rx_pkts[i]->packet_type =
i40e_rxd_pkt_type_mapping(ptype)
;
+ rx_pkts[i]->packet_type =
ptype_tbl[ptype]
;
}
}
}
}
@@
-229,7
+229,7
@@
_recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,
struct i40e_rx_entry *sw_ring;
uint16_t nb_pkts_recd;
int pos;
struct i40e_rx_entry *sw_ring;
uint16_t nb_pkts_recd;
int pos;
- uint
64_t var
;
+ uint
32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl
;
/* mask to shuffle from desc. to mbuf */
uint8x16_t shuf_msk = {
/* mask to shuffle from desc. to mbuf */
uint8x16_t shuf_msk = {
@@
-362,7
+362,6
@@
_recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,
/* C.2 get 4 pkts staterr value */
staterr = vzipq_u16(sterr_tmp1.val[1],
sterr_tmp2.val[1]).val[0];
/* C.2 get 4 pkts staterr value */
staterr = vzipq_u16(sterr_tmp1.val[1],
sterr_tmp2.val[1]).val[0];
- stat = vgetq_lane_u64(vreinterpretq_u64_u16(staterr), 0);
desc_to_olflags_v(rxq, descs, &rx_pkts[pos]);
desc_to_olflags_v(rxq, descs, &rx_pkts[pos]);
@@
-427,6
+426,12
@@
_recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,
rx_pkts[pos + 3]->next = NULL;
}
rx_pkts[pos + 3]->next = NULL;
}
+ staterr = vshlq_n_u16(staterr, I40E_UINT16_BIT - 1);
+ staterr = vreinterpretq_u16_s16(
+ vshrq_n_s16(vreinterpretq_s16_u16(staterr),
+ I40E_UINT16_BIT - 1));
+ stat = ~vgetq_lane_u64(vreinterpretq_u64_u16(staterr), 0);
+
rte_prefetch_non_temporal(rxdp + RTE_I40E_DESCS_PER_LOOP);
/* D.3 copy final 1,2 data to rx_pkts */
rte_prefetch_non_temporal(rxdp + RTE_I40E_DESCS_PER_LOOP);
/* D.3 copy final 1,2 data to rx_pkts */
@@
-434,12
+439,14
@@
_recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,
pkt_mb2);
vst1q_u8((void *)&rx_pkts[pos]->rx_descriptor_fields1,
pkt_mb1);
pkt_mb2);
vst1q_u8((void *)&rx_pkts[pos]->rx_descriptor_fields1,
pkt_mb1);
- desc_to_ptype_v(descs, &rx_pkts[pos]);
+ desc_to_ptype_v(descs, &rx_pkts[pos]
, ptype_tbl
);
/* C.4 calc avaialbe number of desc */
/* C.4 calc avaialbe number of desc */
- var = __builtin_popcountll(stat & I40E_VPMD_DESC_DD_MASK);
- nb_pkts_recd += var;
- if (likely(var != RTE_I40E_DESCS_PER_LOOP))
+ if (unlikely(stat == 0)) {
+ nb_pkts_recd += RTE_I40E_DESCS_PER_LOOP;
+ } else {
+ nb_pkts_recd += __builtin_ctzl(stat) / I40E_UINT16_BIT;
break;
break;
+ }
}
/* Update our internal tail pointer */
}
/* Update our internal tail pointer */
@@
-513,7
+520,7
@@
vtx1(volatile struct i40e_tx_desc *txdp,
((uint64_t)flags << I40E_TXD_QW1_CMD_SHIFT) |
((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT));
((uint64_t)flags << I40E_TXD_QW1_CMD_SHIFT) |
((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT));
- uint64x2_t descriptor = {pkt->buf_
physaddr
+ pkt->data_off, high_qw};
+ uint64x2_t descriptor = {pkt->buf_
iova
+ pkt->data_off, high_qw};
vst1q_u64((uint64_t *)txdp, descriptor);
}
vst1q_u64((uint64_t *)txdp, descriptor);
}