-struct iavf_aqc_remove_tag {
- __le16 seid;
-#define IAVF_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
-#define IAVF_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
- IAVF_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
- __le16 tag;
- u8 reserved[12];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_remove_tag);
-
-/* Add multicast E-Tag (direct 0x0257)
- * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
- * and no external data
- */
-struct iavf_aqc_add_remove_mcast_etag {
- __le16 pv_seid;
- __le16 etag;
- u8 num_unicast_etags;
- u8 reserved[3];
- __le32 addr_high; /* address of array of 2-byte s-tags */
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_mcast_etag);
-
-struct iavf_aqc_add_remove_mcast_etag_completion {
- u8 reserved[4];
- __le16 mcast_etags_used;
- __le16 mcast_etags_free;
- __le32 addr_high;
- __le32 addr_low;
-
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_mcast_etag_completion);
-
-/* Update S/E-Tag (direct 0x0259) */
-struct iavf_aqc_update_tag {
- __le16 seid;
-#define IAVF_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
-#define IAVF_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
- IAVF_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
- __le16 old_tag;
- __le16 new_tag;
- u8 reserved[10];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_update_tag);
-
-struct iavf_aqc_update_tag_completion {
- u8 reserved[12];
- __le16 tags_used;
- __le16 tags_free;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_update_tag_completion);
-
-/* Add Control Packet filter (direct 0x025A)
- * Remove Control Packet filter (direct 0x025B)
- * uses the iavf_aqc_add_oveb_cloud,
- * and the generic direct completion structure
- */
-struct iavf_aqc_add_remove_control_packet_filter {
- u8 mac[6];
- __le16 etype;
- __le16 flags;
-#define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
-#define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
-#define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
-#define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
-#define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
- __le16 seid;
-#define IAVF_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
-#define IAVF_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
- IAVF_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
- __le16 queue;
- u8 reserved[2];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_control_packet_filter);
-
-struct iavf_aqc_add_remove_control_packet_filter_completion {
- __le16 mac_etype_used;
- __le16 etype_used;
- __le16 mac_etype_free;
- __le16 etype_free;
- u8 reserved[8];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_control_packet_filter_completion);
-
-/* Add Cloud filters (indirect 0x025C)
- * Remove Cloud filters (indirect 0x025D)
- * uses the iavf_aqc_add_remove_cloud_filters,
- * and the generic indirect completion structure
- */
-struct iavf_aqc_add_remove_cloud_filters {
- u8 num_filters;
- u8 reserved;
- __le16 seid;
-#define IAVF_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
-#define IAVF_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
- IAVF_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
- u8 big_buffer_flag;
-#define IAVF_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER 1
- u8 reserved2[3];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_cloud_filters);
-
-struct iavf_aqc_add_remove_cloud_filters_element_data {
- u8 outer_mac[6];
- u8 inner_mac[6];
- __le16 inner_vlan;
- union {
- struct {
- u8 reserved[12];
- u8 data[4];
- } v4;
- struct {
- u8 data[16];
- } v6;
- } ipaddr;
- __le16 flags;
-#define IAVF_AQC_ADD_CLOUD_FILTER_SHIFT 0
-#define IAVF_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
- IAVF_AQC_ADD_CLOUD_FILTER_SHIFT)
-/* 0x0000 reserved */
-#define IAVF_AQC_ADD_CLOUD_FILTER_OIP 0x0001
-/* 0x0002 reserved */
-#define IAVF_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
-#define IAVF_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
-/* 0x0005 reserved */
-#define IAVF_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
-/* 0x0007 reserved */
-/* 0x0008 reserved */
-#define IAVF_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
-#define IAVF_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
-#define IAVF_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
-#define IAVF_AQC_ADD_CLOUD_FILTER_IIP 0x000C
-/* 0x0010 to 0x0017 is for custom filters */
-
-#define IAVF_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
-#define IAVF_AQC_ADD_CLOUD_VNK_SHIFT 6
-#define IAVF_AQC_ADD_CLOUD_VNK_MASK 0x00C0
-#define IAVF_AQC_ADD_CLOUD_FLAGS_IPV4 0
-#define IAVF_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
-
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_IP 3
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
-
-#define IAVF_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
-#define IAVF_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
-#define IAVF_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
-
- __le32 tenant_id;
- u8 reserved[4];
- __le16 queue_number;
-#define IAVF_AQC_ADD_CLOUD_QUEUE_SHIFT 0
-#define IAVF_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
- IAVF_AQC_ADD_CLOUD_QUEUE_SHIFT)
- u8 reserved2[14];
- /* response section */
- u8 allocation_result;
-#define IAVF_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
-#define IAVF_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
- u8 response_reserved[7];
-};
-
-/* iavf_aqc_add_rm_cloud_filt_elem_ext is used when
- * IAVF_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER flag is set.
- */
-struct iavf_aqc_add_rm_cloud_filt_elem_ext {
- struct iavf_aqc_add_remove_cloud_filters_element_data element;
- u16 general_fields[32];
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30
-};
-
-struct iavf_aqc_remove_cloud_filters_completion {
- __le16 perfect_ovlan_used;
- __le16 perfect_ovlan_free;
- __le16 vlan_used;
- __le16 vlan_free;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_remove_cloud_filters_completion);
-
-/* Replace filter Command 0x025F
- * uses the iavf_aqc_replace_cloud_filters,
- * and the generic indirect completion structure
- */
-struct iavf_filter_data {
- u8 filter_type;
- u8 input[3];
-};
-
-struct iavf_aqc_replace_cloud_filters_cmd {
- u8 valid_flags;
-#define IAVF_AQC_REPLACE_L1_FILTER 0x0
-#define IAVF_AQC_REPLACE_CLOUD_FILTER 0x1
-#define IAVF_AQC_GET_CLOUD_FILTERS 0x2
-#define IAVF_AQC_MIRROR_CLOUD_FILTER 0x4
-#define IAVF_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8
- u8 old_filter_type;
- u8 new_filter_type;
- u8 tr_bit;
- u8 reserved[4];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-struct iavf_aqc_replace_cloud_filters_cmd_buf {
- u8 data[32];
-/* Filter type INPUT codes*/
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED (1 << 7UL)
-
-/* Field Vector offsets */
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12
-/* big FLU */
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14
-/* big FLU */
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15
-
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37
- struct iavf_filter_data filters[8];
-};
-
-/* Add Mirror Rule (indirect or direct 0x0260)
- * Delete Mirror Rule (indirect or direct 0x0261)
- * note: some rule types (4,5) do not use an external buffer.
- * take care to set the flags correctly.
- */
-struct iavf_aqc_add_delete_mirror_rule {
- __le16 seid;
- __le16 rule_type;
-#define IAVF_AQC_MIRROR_RULE_TYPE_SHIFT 0
-#define IAVF_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
- IAVF_AQC_MIRROR_RULE_TYPE_SHIFT)
-#define IAVF_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
-#define IAVF_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
-#define IAVF_AQC_MIRROR_RULE_TYPE_VLAN 3
-#define IAVF_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
-#define IAVF_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
- __le16 num_entries;
- __le16 destination; /* VSI for add, rule id for delete */
- __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_delete_mirror_rule);
-
-struct iavf_aqc_add_delete_mirror_rule_completion {
- u8 reserved[2];
- __le16 rule_id; /* only used on add */
- __le16 mirror_rules_used;
- __le16 mirror_rules_free;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_delete_mirror_rule_completion);
-
-/* Dynamic Device Personalization */
-struct iavf_aqc_write_personalization_profile {
- u8 flags;
- u8 reserved[3];
- __le32 profile_track_id;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_write_personalization_profile);
-
-struct iavf_aqc_write_ddp_resp {
- __le32 error_offset;
- __le32 error_info;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-struct iavf_aqc_get_applied_profiles {
- u8 flags;
-#define IAVF_AQC_GET_DDP_GET_CONF 0x1
-#define IAVF_AQC_GET_DDP_GET_RDPU_CONF 0x2
- u8 rsv[3];
- __le32 reserved;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_applied_profiles);
-
-/* DCB 0x03xx*/
-
-/* PFC Ignore (direct 0x0301)
- * the command and response use the same descriptor structure
- */
-struct iavf_aqc_pfc_ignore {
- u8 tc_bitmap;
- u8 command_flags; /* unused on response */
-#define IAVF_AQC_PFC_IGNORE_SET 0x80
-#define IAVF_AQC_PFC_IGNORE_CLEAR 0x0
- u8 reserved[14];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_pfc_ignore);
-
-/* DCB Update (direct 0x0302) uses the iavf_aq_desc structure
- * with no parameters
- */
-
-/* TX scheduler 0x04xx */
-
-/* Almost all the indirect commands use
- * this generic struct to pass the SEID in param0
- */
-struct iavf_aqc_tx_sched_ind {
- __le16 vsi_seid;
- u8 reserved[6];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_tx_sched_ind);
-
-/* Several commands respond with a set of queue set handles */
-struct iavf_aqc_qs_handles_resp {
- __le16 qs_handles[8];
-};
-
-/* Configure VSI BW limits (direct 0x0400) */
-struct iavf_aqc_configure_vsi_bw_limit {
- __le16 vsi_seid;
- u8 reserved[2];
- __le16 credit;
- u8 reserved1[2];
- u8 max_credit; /* 0-3, limit = 2^max */
- u8 reserved2[7];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_configure_vsi_bw_limit);
-
-/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
- * responds with iavf_aqc_qs_handles_resp
- */
-struct iavf_aqc_configure_vsi_ets_sla_bw_data {
- u8 tc_valid_bits;
- u8 reserved[15];
- __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
-
- /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
- __le16 tc_bw_max[2];
- u8 reserved1[28];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x40, iavf_aqc_configure_vsi_ets_sla_bw_data);
-
-/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
- * responds with iavf_aqc_qs_handles_resp
- */
-struct iavf_aqc_configure_vsi_tc_bw_data {
- u8 tc_valid_bits;
- u8 reserved[3];
- u8 tc_bw_credits[8];
- u8 reserved1[4];
- __le16 qs_handles[8];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_configure_vsi_tc_bw_data);
-
-/* Query vsi bw configuration (indirect 0x0408) */
-struct iavf_aqc_query_vsi_bw_config_resp {
- u8 tc_valid_bits;
- u8 tc_suspended_bits;
- u8 reserved[14];
- __le16 qs_handles[8];
- u8 reserved1[4];
- __le16 port_bw_limit;
- u8 reserved2[2];
- u8 max_bw; /* 0-3, limit = 2^max */
- u8 reserved3[23];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x40, iavf_aqc_query_vsi_bw_config_resp);
-
-/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
-struct iavf_aqc_query_vsi_ets_sla_config_resp {
- u8 tc_valid_bits;
- u8 reserved[3];
- u8 share_credits[8];
- __le16 credits[8];
-
- /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
- __le16 tc_bw_max[2];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_query_vsi_ets_sla_config_resp);
-
-/* Configure Switching Component Bandwidth Limit (direct 0x0410) */
-struct iavf_aqc_configure_switching_comp_bw_limit {
- __le16 seid;
- u8 reserved[2];
- __le16 credit;
- u8 reserved1[2];
- u8 max_bw; /* 0-3, limit = 2^max */
- u8 reserved2[7];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_configure_switching_comp_bw_limit);
-
-/* Enable Physical Port ETS (indirect 0x0413)
- * Modify Physical Port ETS (indirect 0x0414)
- * Disable Physical Port ETS (indirect 0x0415)
- */
-struct iavf_aqc_configure_switching_comp_ets_data {
- u8 reserved[4];
- u8 tc_valid_bits;
- u8 seepage;
-#define IAVF_AQ_ETS_SEEPAGE_EN_MASK 0x1
- u8 tc_strict_priority_flags;
- u8 reserved1[17];
- u8 tc_bw_share_credits[8];
- u8 reserved2[96];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x80, iavf_aqc_configure_switching_comp_ets_data);
-
-/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
-struct iavf_aqc_configure_switching_comp_ets_bw_limit_data {
- u8 tc_valid_bits;
- u8 reserved[15];
- __le16 tc_bw_credit[8];
-
- /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
- __le16 tc_bw_max[2];
- u8 reserved1[28];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x40,
- iavf_aqc_configure_switching_comp_ets_bw_limit_data);
-
-/* Configure Switching Component Bandwidth Allocation per Tc
- * (indirect 0x0417)
- */
-struct iavf_aqc_configure_switching_comp_bw_config_data {
- u8 tc_valid_bits;
- u8 reserved[2];
- u8 absolute_credits; /* bool */
- u8 tc_bw_share_credits[8];
- u8 reserved1[20];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_configure_switching_comp_bw_config_data);
-
-/* Query Switching Component Configuration (indirect 0x0418) */
-struct iavf_aqc_query_switching_comp_ets_config_resp {
- u8 tc_valid_bits;
- u8 reserved[35];
- __le16 port_bw_limit;
- u8 reserved1[2];
- u8 tc_bw_max; /* 0-3, limit = 2^max */
- u8 reserved2[23];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x40, iavf_aqc_query_switching_comp_ets_config_resp);
-
-/* Query PhysicalPort ETS Configuration (indirect 0x0419) */
-struct iavf_aqc_query_port_ets_config_resp {
- u8 reserved[4];
- u8 tc_valid_bits;
- u8 reserved1;
- u8 tc_strict_priority_bits;
- u8 reserved2;
- u8 tc_bw_share_credits[8];
- __le16 tc_bw_limits[8];
-
- /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
- __le16 tc_bw_max[2];
- u8 reserved3[32];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x44, iavf_aqc_query_port_ets_config_resp);
-
-/* Query Switching Component Bandwidth Allocation per Traffic Type
- * (indirect 0x041A)
- */
-struct iavf_aqc_query_switching_comp_bw_config_resp {
- u8 tc_valid_bits;
- u8 reserved[2];
- u8 absolute_credits_enable; /* bool */
- u8 tc_bw_share_credits[8];
- __le16 tc_bw_limits[8];
-
- /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
- __le16 tc_bw_max[2];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_query_switching_comp_bw_config_resp);
-
-/* Suspend/resume port TX traffic
- * (direct 0x041B and 0x041C) uses the generic SEID struct
- */
-
-/* Configure partition BW
- * (indirect 0x041D)
- */
-struct iavf_aqc_configure_partition_bw_data {
- __le16 pf_valid_bits;
- u8 min_bw[16]; /* guaranteed bandwidth */
- u8 max_bw[16]; /* bandwidth limit */
-};
-
-IAVF_CHECK_STRUCT_LEN(0x22, iavf_aqc_configure_partition_bw_data);
-
-/* Get and set the active HMC resource profile and status.
- * (direct 0x0500) and (direct 0x0501)
- */
-struct iavf_aq_get_set_hmc_resource_profile {
- u8 pm_profile;
- u8 pe_vf_enabled;
- u8 reserved[14];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aq_get_set_hmc_resource_profile);
-
-enum iavf_aq_hmc_profile {
- /* IAVF_HMC_PROFILE_NO_CHANGE = 0, reserved */
- IAVF_HMC_PROFILE_DEFAULT = 1,
- IAVF_HMC_PROFILE_FAVOR_VF = 2,
- IAVF_HMC_PROFILE_EQUAL = 3,
-};
-
-/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
-
-/* set in param0 for get phy abilities to report qualified modules */
-#define IAVF_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
-#define IAVF_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
-
-enum iavf_aq_phy_type {
- IAVF_PHY_TYPE_SGMII = 0x0,
- IAVF_PHY_TYPE_1000BASE_KX = 0x1,
- IAVF_PHY_TYPE_10GBASE_KX4 = 0x2,
- IAVF_PHY_TYPE_10GBASE_KR = 0x3,
- IAVF_PHY_TYPE_40GBASE_KR4 = 0x4,
- IAVF_PHY_TYPE_XAUI = 0x5,
- IAVF_PHY_TYPE_XFI = 0x6,
- IAVF_PHY_TYPE_SFI = 0x7,
- IAVF_PHY_TYPE_XLAUI = 0x8,
- IAVF_PHY_TYPE_XLPPI = 0x9,
- IAVF_PHY_TYPE_40GBASE_CR4_CU = 0xA,
- IAVF_PHY_TYPE_10GBASE_CR1_CU = 0xB,
- IAVF_PHY_TYPE_10GBASE_AOC = 0xC,
- IAVF_PHY_TYPE_40GBASE_AOC = 0xD,
- IAVF_PHY_TYPE_UNRECOGNIZED = 0xE,
- IAVF_PHY_TYPE_UNSUPPORTED = 0xF,
- IAVF_PHY_TYPE_100BASE_TX = 0x11,
- IAVF_PHY_TYPE_1000BASE_T = 0x12,
- IAVF_PHY_TYPE_10GBASE_T = 0x13,
- IAVF_PHY_TYPE_10GBASE_SR = 0x14,
- IAVF_PHY_TYPE_10GBASE_LR = 0x15,
- IAVF_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
- IAVF_PHY_TYPE_10GBASE_CR1 = 0x17,
- IAVF_PHY_TYPE_40GBASE_CR4 = 0x18,
- IAVF_PHY_TYPE_40GBASE_SR4 = 0x19,
- IAVF_PHY_TYPE_40GBASE_LR4 = 0x1A,
- IAVF_PHY_TYPE_1000BASE_SX = 0x1B,
- IAVF_PHY_TYPE_1000BASE_LX = 0x1C,
- IAVF_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
- IAVF_PHY_TYPE_20GBASE_KR2 = 0x1E,
- IAVF_PHY_TYPE_25GBASE_KR = 0x1F,
- IAVF_PHY_TYPE_25GBASE_CR = 0x20,
- IAVF_PHY_TYPE_25GBASE_SR = 0x21,
- IAVF_PHY_TYPE_25GBASE_LR = 0x22,
- IAVF_PHY_TYPE_25GBASE_AOC = 0x23,
- IAVF_PHY_TYPE_25GBASE_ACC = 0x24,
- IAVF_PHY_TYPE_MAX,
- IAVF_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
- IAVF_PHY_TYPE_EMPTY = 0xFE,
- IAVF_PHY_TYPE_DEFAULT = 0xFF,
-};
-
-#define IAVF_LINK_SPEED_100MB_SHIFT 0x1
-#define IAVF_LINK_SPEED_1000MB_SHIFT 0x2
-#define IAVF_LINK_SPEED_10GB_SHIFT 0x3
-#define IAVF_LINK_SPEED_40GB_SHIFT 0x4
-#define IAVF_LINK_SPEED_20GB_SHIFT 0x5
-#define IAVF_LINK_SPEED_25GB_SHIFT 0x6
-
-enum iavf_aq_link_speed {
- IAVF_LINK_SPEED_UNKNOWN = 0,
- IAVF_LINK_SPEED_100MB = (1 << IAVF_LINK_SPEED_100MB_SHIFT),
- IAVF_LINK_SPEED_1GB = (1 << IAVF_LINK_SPEED_1000MB_SHIFT),
- IAVF_LINK_SPEED_10GB = (1 << IAVF_LINK_SPEED_10GB_SHIFT),
- IAVF_LINK_SPEED_40GB = (1 << IAVF_LINK_SPEED_40GB_SHIFT),
- IAVF_LINK_SPEED_20GB = (1 << IAVF_LINK_SPEED_20GB_SHIFT),
- IAVF_LINK_SPEED_25GB = (1 << IAVF_LINK_SPEED_25GB_SHIFT),
-};
-
-struct iavf_aqc_module_desc {
- u8 oui[3];
- u8 reserved1;
- u8 part_number[16];
- u8 revision[4];
- u8 reserved2[8];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_module_desc);
-
-struct iavf_aq_get_phy_abilities_resp {
- __le32 phy_type; /* bitmap using the above enum for offsets */
- u8 link_speed; /* bitmap using the above enum bit patterns */
- u8 abilities;
-#define IAVF_AQ_PHY_FLAG_PAUSE_TX 0x01
-#define IAVF_AQ_PHY_FLAG_PAUSE_RX 0x02
-#define IAVF_AQ_PHY_FLAG_LOW_POWER 0x04
-#define IAVF_AQ_PHY_LINK_ENABLED 0x08
-#define IAVF_AQ_PHY_AN_ENABLED 0x10
-#define IAVF_AQ_PHY_FLAG_MODULE_QUAL 0x20
-#define IAVF_AQ_PHY_FEC_ABILITY_KR 0x40
-#define IAVF_AQ_PHY_FEC_ABILITY_RS 0x80
- __le16 eee_capability;
-#define IAVF_AQ_EEE_100BASE_TX 0x0002
-#define IAVF_AQ_EEE_1000BASE_T 0x0004
-#define IAVF_AQ_EEE_10GBASE_T 0x0008
-#define IAVF_AQ_EEE_1000BASE_KX 0x0010
-#define IAVF_AQ_EEE_10GBASE_KX4 0x0020
-#define IAVF_AQ_EEE_10GBASE_KR 0x0040
- __le32 eeer_val;
- u8 d3_lpan;
-#define IAVF_AQ_SET_PHY_D3_LPAN_ENA 0x01
- u8 phy_type_ext;
-#define IAVF_AQ_PHY_TYPE_EXT_25G_KR 0x01
-#define IAVF_AQ_PHY_TYPE_EXT_25G_CR 0x02
-#define IAVF_AQ_PHY_TYPE_EXT_25G_SR 0x04
-#define IAVF_AQ_PHY_TYPE_EXT_25G_LR 0x08
-#define IAVF_AQ_PHY_TYPE_EXT_25G_AOC 0x10
-#define IAVF_AQ_PHY_TYPE_EXT_25G_ACC 0x20
- u8 fec_cfg_curr_mod_ext_info;
-#define IAVF_AQ_ENABLE_FEC_KR 0x01
-#define IAVF_AQ_ENABLE_FEC_RS 0x02
-#define IAVF_AQ_REQUEST_FEC_KR 0x04
-#define IAVF_AQ_REQUEST_FEC_RS 0x08
-#define IAVF_AQ_ENABLE_FEC_AUTO 0x10
-#define IAVF_AQ_FEC
-#define IAVF_AQ_MODULE_TYPE_EXT_MASK 0xE0
-#define IAVF_AQ_MODULE_TYPE_EXT_SHIFT 5
-
- u8 ext_comp_code;
- u8 phy_id[4];
- u8 module_type[3];
- u8 qualified_module_count;
-#define IAVF_AQ_PHY_MAX_QMS 16
- struct iavf_aqc_module_desc qualified_module[IAVF_AQ_PHY_MAX_QMS];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x218, iavf_aq_get_phy_abilities_resp);
-
-/* Set PHY Config (direct 0x0601) */
-struct iavf_aq_set_phy_config { /* same bits as above in all */
- __le32 phy_type;
- u8 link_speed;
- u8 abilities;
-/* bits 0-2 use the values from get_phy_abilities_resp */
-#define IAVF_AQ_PHY_ENABLE_LINK 0x08
-#define IAVF_AQ_PHY_ENABLE_AN 0x10
-#define IAVF_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
- __le16 eee_capability;
- __le32 eeer;
- u8 low_power_ctrl;
- u8 phy_type_ext;
- u8 fec_config;
-#define IAVF_AQ_SET_FEC_ABILITY_KR BIT(0)
-#define IAVF_AQ_SET_FEC_ABILITY_RS BIT(1)
-#define IAVF_AQ_SET_FEC_REQUEST_KR BIT(2)
-#define IAVF_AQ_SET_FEC_REQUEST_RS BIT(3)
-#define IAVF_AQ_SET_FEC_AUTO BIT(4)
-#define IAVF_AQ_PHY_FEC_CONFIG_SHIFT 0x0
-#define IAVF_AQ_PHY_FEC_CONFIG_MASK (0x1F << IAVF_AQ_PHY_FEC_CONFIG_SHIFT)
- u8 reserved;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aq_set_phy_config);
-
-/* Set MAC Config command data structure (direct 0x0603) */
-struct iavf_aq_set_mac_config {
- __le16 max_frame_size;
- u8 params;
-#define IAVF_AQ_SET_MAC_CONFIG_CRC_EN 0x04
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
- u8 tx_timer_priority; /* bitmap */
- __le16 tx_timer_value;
- __le16 fc_refresh_threshold;
- u8 reserved[8];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aq_set_mac_config);
-
-/* Restart Auto-Negotiation (direct 0x605) */
-struct iavf_aqc_set_link_restart_an {
- u8 command;
-#define IAVF_AQ_PHY_RESTART_AN 0x02
-#define IAVF_AQ_PHY_LINK_ENABLE 0x04
- u8 reserved[15];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_link_restart_an);
-
-/* Get Link Status cmd & response data structure (direct 0x0607) */
-struct iavf_aqc_get_link_status {
- __le16 command_flags; /* only field set on command */
-#define IAVF_AQ_LSE_MASK 0x3
-#define IAVF_AQ_LSE_NOP 0x0
-#define IAVF_AQ_LSE_DISABLE 0x2
-#define IAVF_AQ_LSE_ENABLE 0x3
-/* only response uses this flag */
-#define IAVF_AQ_LSE_IS_ENABLED 0x1
- u8 phy_type; /* iavf_aq_phy_type */
- u8 link_speed; /* iavf_aq_link_speed */
- u8 link_info;
-#define IAVF_AQ_LINK_UP 0x01 /* obsolete */
-#define IAVF_AQ_LINK_UP_FUNCTION 0x01
-#define IAVF_AQ_LINK_FAULT 0x02
-#define IAVF_AQ_LINK_FAULT_TX 0x04
-#define IAVF_AQ_LINK_FAULT_RX 0x08
-#define IAVF_AQ_LINK_FAULT_REMOTE 0x10
-#define IAVF_AQ_LINK_UP_PORT 0x20
-#define IAVF_AQ_MEDIA_AVAILABLE 0x40
-#define IAVF_AQ_SIGNAL_DETECT 0x80
- u8 an_info;
-#define IAVF_AQ_AN_COMPLETED 0x01
-#define IAVF_AQ_LP_AN_ABILITY 0x02
-#define IAVF_AQ_PD_FAULT 0x04
-#define IAVF_AQ_FEC_EN 0x08
-#define IAVF_AQ_PHY_LOW_POWER 0x10
-#define IAVF_AQ_LINK_PAUSE_TX 0x20
-#define IAVF_AQ_LINK_PAUSE_RX 0x40
-#define IAVF_AQ_QUALIFIED_MODULE 0x80
- u8 ext_info;
-#define IAVF_AQ_LINK_PHY_TEMP_ALARM 0x01
-#define IAVF_AQ_LINK_XCESSIVE_ERRORS 0x02
-#define IAVF_AQ_LINK_TX_SHIFT 0x02
-#define IAVF_AQ_LINK_TX_MASK (0x03 << IAVF_AQ_LINK_TX_SHIFT)
-#define IAVF_AQ_LINK_TX_ACTIVE 0x00
-#define IAVF_AQ_LINK_TX_DRAINED 0x01
-#define IAVF_AQ_LINK_TX_FLUSHED 0x03
-#define IAVF_AQ_LINK_FORCED_40G 0x10
-/* 25G Error Codes */
-#define IAVF_AQ_25G_NO_ERR 0X00
-#define IAVF_AQ_25G_NOT_PRESENT 0X01
-#define IAVF_AQ_25G_NVM_CRC_ERR 0X02
-#define IAVF_AQ_25G_SBUS_UCODE_ERR 0X03
-#define IAVF_AQ_25G_SERDES_UCODE_ERR 0X04
-#define IAVF_AQ_25G_NIMB_UCODE_ERR 0X05
- u8 loopback; /* use defines from iavf_aqc_set_lb_mode */
-/* Since firmware API 1.7 loopback field keeps power class info as well */
-#define IAVF_AQ_LOOPBACK_MASK 0x07
-#define IAVF_AQ_PWR_CLASS_SHIFT_LB 6
-#define IAVF_AQ_PWR_CLASS_MASK_LB (0x03 << IAVF_AQ_PWR_CLASS_SHIFT_LB)
- __le16 max_frame_size;
- u8 config;
-#define IAVF_AQ_CONFIG_FEC_KR_ENA 0x01
-#define IAVF_AQ_CONFIG_FEC_RS_ENA 0x02
-#define IAVF_AQ_CONFIG_CRC_ENA 0x04
-#define IAVF_AQ_CONFIG_PACING_MASK 0x78
- union {
- struct {
- u8 power_desc;
-#define IAVF_AQ_LINK_POWER_CLASS_1 0x00
-#define IAVF_AQ_LINK_POWER_CLASS_2 0x01
-#define IAVF_AQ_LINK_POWER_CLASS_3 0x02
-#define IAVF_AQ_LINK_POWER_CLASS_4 0x03
-#define IAVF_AQ_PWR_CLASS_MASK 0x03
- u8 reserved[4];
- };
- struct {
- u8 link_type[4];
- u8 link_type_ext;
- };
- };
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_link_status);
-
-/* Set event mask command (direct 0x613) */
-struct iavf_aqc_set_phy_int_mask {
- u8 reserved[8];
- __le16 event_mask;
-#define IAVF_AQ_EVENT_LINK_UPDOWN 0x0002
-#define IAVF_AQ_EVENT_MEDIA_NA 0x0004
-#define IAVF_AQ_EVENT_LINK_FAULT 0x0008
-#define IAVF_AQ_EVENT_PHY_TEMP_ALARM 0x0010
-#define IAVF_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
-#define IAVF_AQ_EVENT_SIGNAL_DETECT 0x0040
-#define IAVF_AQ_EVENT_AN_COMPLETED 0x0080
-#define IAVF_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
-#define IAVF_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
- u8 reserved1[6];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_phy_int_mask);
-
-/* Get Local AN advt register (direct 0x0614)
- * Set Local AN advt register (direct 0x0615)
- * Get Link Partner AN advt register (direct 0x0616)
- */
-struct iavf_aqc_an_advt_reg {
- __le32 local_an_reg0;
- __le16 local_an_reg1;
- u8 reserved[10];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_an_advt_reg);
-
-/* Set Loopback mode (0x0618) */
-struct iavf_aqc_set_lb_mode {
- u8 lb_level;
-#define IAVF_AQ_LB_NONE 0
-#define IAVF_AQ_LB_MAC 1
-#define IAVF_AQ_LB_SERDES 2
-#define IAVF_AQ_LB_PHY_INT 3
-#define IAVF_AQ_LB_PHY_EXT 4
-#define IAVF_AQ_LB_CPVL_PCS 5
-#define IAVF_AQ_LB_CPVL_EXT 6
-#define IAVF_AQ_LB_PHY_LOCAL 0x01
-#define IAVF_AQ_LB_PHY_REMOTE 0x02
-#define IAVF_AQ_LB_MAC_LOCAL 0x04
- u8 lb_type;
-#define IAVF_AQ_LB_LOCAL 0
-#define IAVF_AQ_LB_FAR 0x01
- u8 speed;
-#define IAVF_AQ_LB_SPEED_NONE 0
-#define IAVF_AQ_LB_SPEED_1G 1
-#define IAVF_AQ_LB_SPEED_10G 2
-#define IAVF_AQ_LB_SPEED_40G 3
-#define IAVF_AQ_LB_SPEED_20G 4
- u8 force_speed;
- u8 reserved[12];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_lb_mode);
-
-/* Set PHY Debug command (0x0622) */
-struct iavf_aqc_set_phy_debug {
- u8 command_flags;
-#define IAVF_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
-#define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
-#define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
- IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
-#define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
-#define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
-#define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
-/* Disable link manageability on a single port */
-#define IAVF_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
-/* Disable link manageability on all ports needs both bits 4 and 5 */
-#define IAVF_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
- u8 reserved[15];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_phy_debug);
-
-enum iavf_aq_phy_reg_type {
- IAVF_AQC_PHY_REG_INTERNAL = 0x1,
- IAVF_AQC_PHY_REG_EXERNAL_BASET = 0x2,
- IAVF_AQC_PHY_REG_EXERNAL_MODULE = 0x3
-};
-
-/* Run PHY Activity (0x0626) */
-struct iavf_aqc_run_phy_activity {
- __le16 activity_id;
- u8 flags;
- u8 reserved1;
- __le32 control;
- __le32 data;
- u8 reserved2[4];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_run_phy_activity);
-
-/* Set PHY Register command (0x0628) */
-/* Get PHY Register command (0x0629) */
-struct iavf_aqc_phy_register_access {
- u8 phy_interface;
-#define IAVF_AQ_PHY_REG_ACCESS_INTERNAL 0
-#define IAVF_AQ_PHY_REG_ACCESS_EXTERNAL 1
-#define IAVF_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2
- u8 dev_addres;
- u8 reserved1[2];
- __le32 reg_address;
- __le32 reg_value;
- u8 reserved2[4];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_phy_register_access);
-
-/* NVM Read command (indirect 0x0701)
- * NVM Erase commands (direct 0x0702)
- * NVM Update commands (indirect 0x0703)
- */
-struct iavf_aqc_nvm_update {
- u8 command_flags;
-#define IAVF_AQ_NVM_LAST_CMD 0x01
-#define IAVF_AQ_NVM_FLASH_ONLY 0x80
-#define IAVF_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1
-#define IAVF_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03
-#define IAVF_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
-#define IAVF_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01
- u8 module_pointer;
- __le16 length;
- __le32 offset;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_nvm_update);
-
-/* NVM Config Read (indirect 0x0704) */
-struct iavf_aqc_nvm_config_read {
- __le16 cmd_flags;
-#define IAVF_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
-#define IAVF_AQ_ANVM_READ_SINGLE_FEATURE 0
-#define IAVF_AQ_ANVM_READ_MULTIPLE_FEATURES 1
- __le16 element_count;
- __le16 element_id; /* Feature/field ID */
- __le16 element_id_msw; /* MSWord of field ID */
- __le32 address_high;
- __le32 address_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_nvm_config_read);
-
-/* NVM Config Write (indirect 0x0705) */
-struct iavf_aqc_nvm_config_write {
- __le16 cmd_flags;
- __le16 element_count;
- u8 reserved[4];
- __le32 address_high;
- __le32 address_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_nvm_config_write);
-
-/* Used for 0x0704 as well as for 0x0705 commands */
-#define IAVF_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
-#define IAVF_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
- (1 << IAVF_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
-#define IAVF_AQ_ANVM_FEATURE 0
-#define IAVF_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
-struct iavf_aqc_nvm_config_data_feature {
- __le16 feature_id;
-#define IAVF_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
-#define IAVF_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
-#define IAVF_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
- __le16 feature_options;
- __le16 feature_selection;
-};
-
-IAVF_CHECK_STRUCT_LEN(0x6, iavf_aqc_nvm_config_data_feature);
-
-struct iavf_aqc_nvm_config_data_immediate_field {
- __le32 field_id;
- __le32 field_value;
- __le16 field_options;
- __le16 reserved;
-};
-
-IAVF_CHECK_STRUCT_LEN(0xc, iavf_aqc_nvm_config_data_immediate_field);
-
-/* OEM Post Update (indirect 0x0720)
- * no command data struct used
- */
-struct iavf_aqc_nvm_oem_post_update {
-#define IAVF_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
- u8 sel_data;
- u8 reserved[7];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x8, iavf_aqc_nvm_oem_post_update);
-
-struct iavf_aqc_nvm_oem_post_update_buffer {
- u8 str_len;
- u8 dev_addr;
- __le16 eeprom_addr;
- u8 data[36];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x28, iavf_aqc_nvm_oem_post_update_buffer);
-
-/* Thermal Sensor (indirect 0x0721)
- * read or set thermal sensor configs and values
- * takes a sensor and command specific data buffer, not detailed here
- */
-struct iavf_aqc_thermal_sensor {
- u8 sensor_action;
-#define IAVF_AQ_THERMAL_SENSOR_READ_CONFIG 0
-#define IAVF_AQ_THERMAL_SENSOR_SET_CONFIG 1
-#define IAVF_AQ_THERMAL_SENSOR_READ_TEMP 2
- u8 reserved[7];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_thermal_sensor);
-
-/* Send to PF command (indirect 0x0801) id is only used by PF
- * Send to VF command (indirect 0x0802) id is only used by PF
- * Send to Peer PF command (indirect 0x0803)
- */
-struct iavf_aqc_pf_vf_message {
- __le32 id;
- u8 reserved[4];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_pf_vf_message);
-
-/* Alternate structure */
-
-/* Direct write (direct 0x0900)
- * Direct read (direct 0x0902)
- */
-struct iavf_aqc_alternate_write {
- __le32 address0;
- __le32 data0;
- __le32 address1;
- __le32 data1;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_write);
-
-/* Indirect write (indirect 0x0901)
- * Indirect read (indirect 0x0903)
- */
-
-struct iavf_aqc_alternate_ind_write {
- __le32 address;
- __le32 length;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_ind_write);
-
-/* Done alternate write (direct 0x0904)
- * uses iavf_aq_desc
- */
-struct iavf_aqc_alternate_write_done {
- __le16 cmd_flags;
-#define IAVF_AQ_ALTERNATE_MODE_BIOS_MASK 1
-#define IAVF_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
-#define IAVF_AQ_ALTERNATE_MODE_BIOS_UEFI 1
-#define IAVF_AQ_ALTERNATE_RESET_NEEDED 2
- u8 reserved[14];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_write_done);
-
-/* Set OEM mode (direct 0x0905) */
-struct iavf_aqc_alternate_set_mode {
- __le32 mode;
-#define IAVF_AQ_ALTERNATE_MODE_NONE 0
-#define IAVF_AQ_ALTERNATE_MODE_OEM 1
- u8 reserved[12];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_set_mode);
-
-/* Clear port Alternate RAM (direct 0x0906) uses iavf_aq_desc */
-
-/* async events 0x10xx */
-
-/* Lan Queue Overflow Event (direct, 0x1001) */
-struct iavf_aqc_lan_overflow {
- __le32 prtdcb_rupto;
- __le32 otx_ctl;
- u8 reserved[8];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lan_overflow);
-
-/* Get LLDP MIB (indirect 0x0A00) */
-struct iavf_aqc_lldp_get_mib {
- u8 type;
- u8 reserved1;
-#define IAVF_AQ_LLDP_MIB_TYPE_MASK 0x3
-#define IAVF_AQ_LLDP_MIB_LOCAL 0x0
-#define IAVF_AQ_LLDP_MIB_REMOTE 0x1
-#define IAVF_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
-#define IAVF_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
-#define IAVF_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
-#define IAVF_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
-#define IAVF_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
-#define IAVF_AQ_LLDP_TX_SHIFT 0x4
-#define IAVF_AQ_LLDP_TX_MASK (0x03 << IAVF_AQ_LLDP_TX_SHIFT)
-/* TX pause flags use IAVF_AQ_LINK_TX_* above */
- __le16 local_len;
- __le16 remote_len;
- u8 reserved2[2];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_get_mib);
-
-/* Configure LLDP MIB Change Event (direct 0x0A01)
- * also used for the event (with type in the command field)
- */
-struct iavf_aqc_lldp_update_mib {
- u8 command;
-#define IAVF_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
-#define IAVF_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
- u8 reserved[7];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_update_mib);
-
-/* Add LLDP TLV (indirect 0x0A02)
- * Delete LLDP TLV (indirect 0x0A04)
- */
-struct iavf_aqc_lldp_add_tlv {
- u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
- u8 reserved1[1];
- __le16 len;
- u8 reserved2[4];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_add_tlv);
-
-/* Update LLDP TLV (indirect 0x0A03) */
-struct iavf_aqc_lldp_update_tlv {
- u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
- u8 reserved;
- __le16 old_len;
- __le16 new_offset;
- __le16 new_len;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_update_tlv);
-
-/* Stop LLDP (direct 0x0A05) */
-struct iavf_aqc_lldp_stop {
- u8 command;
-#define IAVF_AQ_LLDP_AGENT_STOP 0x0
-#define IAVF_AQ_LLDP_AGENT_SHUTDOWN 0x1
- u8 reserved[15];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_stop);
-
-/* Start LLDP (direct 0x0A06) */
-
-struct iavf_aqc_lldp_start {
- u8 command;
-#define IAVF_AQ_LLDP_AGENT_START 0x1
- u8 reserved[15];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_start);
-
-/* Set DCB (direct 0x0303) */
-struct iavf_aqc_set_dcb_parameters {
- u8 command;
-#define IAVF_AQ_DCB_SET_AGENT 0x1
-#define IAVF_DCB_VALID 0x1
- u8 valid_flags;
- u8 reserved[14];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_dcb_parameters);
-
-/* Get CEE DCBX Oper Config (0x0A07)
- * uses the generic descriptor struct
- * returns below as indirect response
- */
-
-#define IAVF_AQC_CEE_APP_FCOE_SHIFT 0x0
-#define IAVF_AQC_CEE_APP_FCOE_MASK (0x7 << IAVF_AQC_CEE_APP_FCOE_SHIFT)
-#define IAVF_AQC_CEE_APP_ISCSI_SHIFT 0x3
-#define IAVF_AQC_CEE_APP_ISCSI_MASK (0x7 << IAVF_AQC_CEE_APP_ISCSI_SHIFT)
-#define IAVF_AQC_CEE_APP_FIP_SHIFT 0x8
-#define IAVF_AQC_CEE_APP_FIP_MASK (0x7 << IAVF_AQC_CEE_APP_FIP_SHIFT)
-
-#define IAVF_AQC_CEE_PG_STATUS_SHIFT 0x0
-#define IAVF_AQC_CEE_PG_STATUS_MASK (0x7 << IAVF_AQC_CEE_PG_STATUS_SHIFT)
-#define IAVF_AQC_CEE_PFC_STATUS_SHIFT 0x3
-#define IAVF_AQC_CEE_PFC_STATUS_MASK (0x7 << IAVF_AQC_CEE_PFC_STATUS_SHIFT)
-#define IAVF_AQC_CEE_APP_STATUS_SHIFT 0x8
-#define IAVF_AQC_CEE_APP_STATUS_MASK (0x7 << IAVF_AQC_CEE_APP_STATUS_SHIFT)
-#define IAVF_AQC_CEE_FCOE_STATUS_SHIFT 0x8
-#define IAVF_AQC_CEE_FCOE_STATUS_MASK (0x7 << IAVF_AQC_CEE_FCOE_STATUS_SHIFT)
-#define IAVF_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
-#define IAVF_AQC_CEE_ISCSI_STATUS_MASK (0x7 << IAVF_AQC_CEE_ISCSI_STATUS_SHIFT)
-#define IAVF_AQC_CEE_FIP_STATUS_SHIFT 0x10
-#define IAVF_AQC_CEE_FIP_STATUS_MASK (0x7 << IAVF_AQC_CEE_FIP_STATUS_SHIFT)
-
-/* struct iavf_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
- * word boundary layout issues, which the Linux compilers silently deal
- * with by adding padding, making the actual struct larger than designed.
- * However, the FW compiler for the NIC is less lenient and complains
- * about the struct. Hence, the struct defined here has an extra byte in
- * fields reserved3 and reserved4 to directly acknowledge that padding,
- * and the new length is used in the length check macro.
- */
-struct iavf_aqc_get_cee_dcb_cfg_v1_resp {
- u8 reserved1;
- u8 oper_num_tc;
- u8 oper_prio_tc[4];
- u8 reserved2;
- u8 oper_tc_bw[8];
- u8 oper_pfc_en;
- u8 reserved3[2];
- __le16 oper_app_prio;
- u8 reserved4[2];
- __le16 tlv_status;
-};
-
-IAVF_CHECK_STRUCT_LEN(0x18, iavf_aqc_get_cee_dcb_cfg_v1_resp);
-
-struct iavf_aqc_get_cee_dcb_cfg_resp {
- u8 oper_num_tc;
- u8 oper_prio_tc[4];
- u8 oper_tc_bw[8];
- u8 oper_pfc_en;
- __le16 oper_app_prio;
- __le32 tlv_status;
- u8 reserved[12];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_get_cee_dcb_cfg_resp);
-
-/* Set Local LLDP MIB (indirect 0x0A08)
- * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
- */
-struct iavf_aqc_lldp_set_local_mib {
-#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
-#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
- SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
-#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
-#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
-#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
- SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
-#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
- u8 type;
- u8 reserved0;
- __le16 length;
- u8 reserved1[4];
- __le32 address_high;
- __le32 address_low;