+ case RTE_FLOW_ITEM_TYPE_GTPU:
+ gtp_spec = item->spec;
+ gtp_mask = item->mask;
+
+ hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
+
+ VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, GTPU_IP);
+
+ if (gtp_spec && gtp_mask) {
+ if (gtp_mask->v_pt_rsv_flags ||
+ gtp_mask->msg_type ||
+ gtp_mask->msg_len) {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ITEM,
+ item, "Invalid GTP mask");
+ return -rte_errno;
+ }
+
+ if (gtp_mask->teid == UINT32_MAX) {
+ input_set |= IAVF_INSET_GTPU_TEID;
+ VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, GTPU_IP, TEID);
+ }
+
+ rte_memcpy(hdr->buffer,
+ gtp_spec, sizeof(*gtp_spec));
+ }
+
+ filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
+ break;
+
+ case RTE_FLOW_ITEM_TYPE_GTP_PSC:
+ gtp_psc_spec = item->spec;
+ gtp_psc_mask = item->mask;
+
+ hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
+
+ VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, GTPU_EH);
+
+ if (gtp_psc_spec && gtp_psc_mask) {
+ if (gtp_psc_mask->qfi == UINT8_MAX) {
+ input_set |= IAVF_INSET_GTPU_QFI;
+ VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, GTPU_EH, QFI);
+ }
+
+ rte_memcpy(hdr->buffer, gtp_psc_spec,
+ sizeof(*gtp_psc_spec));
+ }
+
+ filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
+ break;
+
+ case RTE_FLOW_ITEM_TYPE_L2TPV3OIP:
+ l2tpv3oip_spec = item->spec;
+ l2tpv3oip_mask = item->mask;
+
+ hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
+
+ VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, L2TPV3);
+
+ if (l2tpv3oip_spec && l2tpv3oip_mask) {
+ if (l2tpv3oip_mask->session_id == UINT32_MAX) {
+ input_set |= IAVF_L2TPV3OIP_SESSION_ID;
+ VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, L2TPV3, SESS_ID);
+ }
+
+ rte_memcpy(hdr->buffer, l2tpv3oip_spec,
+ sizeof(*l2tpv3oip_spec));
+ }
+
+ filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
+ break;
+
+ case RTE_FLOW_ITEM_TYPE_ESP:
+ esp_spec = item->spec;
+ esp_mask = item->mask;
+
+ hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
+
+ VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, ESP);
+
+ if (esp_spec && esp_mask) {
+ if (esp_mask->hdr.spi == UINT32_MAX) {
+ input_set |= IAVF_INSET_ESP_SPI;
+ VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, ESP, SPI);
+ }
+
+ rte_memcpy(hdr->buffer, &esp_spec->hdr,
+ sizeof(esp_spec->hdr));
+ }
+
+ filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
+ break;
+
+ case RTE_FLOW_ITEM_TYPE_AH:
+ ah_spec = item->spec;
+ ah_mask = item->mask;
+
+ hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
+
+ VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, AH);
+
+ if (ah_spec && ah_mask) {
+ if (ah_mask->spi == UINT32_MAX) {
+ input_set |= IAVF_INSET_AH_SPI;
+ VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, AH, SPI);
+ }
+
+ rte_memcpy(hdr->buffer, ah_spec,
+ sizeof(*ah_spec));
+ }
+
+ filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
+ break;
+
+ case RTE_FLOW_ITEM_TYPE_PFCP:
+ pfcp_spec = item->spec;
+ pfcp_mask = item->mask;
+
+ hdr = &filter->add_fltr.rule_cfg.proto_hdrs.proto_hdr[layer];
+
+ VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, PFCP);
+
+ if (pfcp_spec && pfcp_mask) {
+ if (pfcp_mask->s_field == UINT8_MAX) {
+ input_set |= IAVF_INSET_PFCP_S_FIELD;
+ VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, PFCP, S_FIELD);
+ }
+
+ rte_memcpy(hdr->buffer, pfcp_spec,
+ sizeof(*pfcp_spec));
+ }
+
+ filter->add_fltr.rule_cfg.proto_hdrs.count = ++layer;
+ break;
+