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net/mlx5: support more tunnel types
[dpdk.git]
/
drivers
/
net
/
ice
/
base
/
ice_controlq.h
diff --git
a/drivers/net/ice/base/ice_controlq.h
b/drivers/net/ice/base/ice_controlq.h
index
8b60465
..
840fb5e
100644
(file)
--- a/
drivers/net/ice/base/ice_controlq.h
+++ b/
drivers/net/ice/base/ice_controlq.h
@@
-1,5
+1,5
@@
/* SPDX-License-Identifier: BSD-3-Clause
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-20
19
+ * Copyright(c) 2001-20
21 Intel Corporation
*/
#ifndef _ICE_CONTROLQ_H_
*/
#ifndef _ICE_CONTROLQ_H_
@@
-10,13
+10,14
@@
/* Maximum buffer lengths for all control queue types */
#define ICE_AQ_MAX_BUF_LEN 4096
#define ICE_MBXQ_MAX_BUF_LEN 4096
/* Maximum buffer lengths for all control queue types */
#define ICE_AQ_MAX_BUF_LEN 4096
#define ICE_MBXQ_MAX_BUF_LEN 4096
+#define ICE_SBQ_MAX_BUF_LEN 512
#define ICE_CTL_Q_DESC(R, i) \
(&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))
#define ICE_CTL_Q_DESC_UNUSED(R) \
#define ICE_CTL_Q_DESC(R, i) \
(&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))
#define ICE_CTL_Q_DESC_UNUSED(R) \
- (u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
-
(R)->next_to_clean - (R)->next_to_use - 1
)
+ (
(
u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
+
(R)->next_to_clean - (R)->next_to_use - 1)
)
/* Defines that help manage the driver vs FW API checks.
* Take a look at ice_aq_ver_check in ice_controlq.c for actual usage.
/* Defines that help manage the driver vs FW API checks.
* Take a look at ice_aq_ver_check in ice_controlq.c for actual usage.
@@
-30,11
+31,14
@@
enum ice_ctl_q {
ICE_CTL_Q_UNKNOWN = 0,
ICE_CTL_Q_ADMIN,
ICE_CTL_Q_MAILBOX,
ICE_CTL_Q_UNKNOWN = 0,
ICE_CTL_Q_ADMIN,
ICE_CTL_Q_MAILBOX,
+ ICE_CTL_Q_SB,
};
};
-/* Control Queue timeout settings - max delay
250m
s */
-#define ICE_CTL_Q_SQ_CMD_TIMEOUT
2500 /* Count 25
00 times */
+/* Control Queue timeout settings - max delay
1
s */
+#define ICE_CTL_Q_SQ_CMD_TIMEOUT
10000 /* Count 100
00 times */
#define ICE_CTL_Q_SQ_CMD_USEC 100 /* Check every 100usec */
#define ICE_CTL_Q_SQ_CMD_USEC 100 /* Check every 100usec */
+#define ICE_CTL_Q_ADMIN_INIT_TIMEOUT 10 /* Count 10 times */
+#define ICE_CTL_Q_ADMIN_INIT_MSEC 100 /* Check every 100msec */
struct ice_ctl_q_ring {
void *dma_head; /* Virtual address to DMA head */
struct ice_ctl_q_ring {
void *dma_head; /* Virtual address to DMA head */
@@
-60,6
+64,7
@@
struct ice_ctl_q_ring {
u32 bal;
u32 len_mask;
u32 len_ena_mask;
u32 bal;
u32 len_mask;
u32 len_ena_mask;
+ u32 len_crit_mask;
u32 head_mask;
};
u32 head_mask;
};
@@
-81,7
+86,6
@@
struct ice_rq_event_info {
/* Control Queue information */
struct ice_ctl_q_info {
enum ice_ctl_q qtype;
/* Control Queue information */
struct ice_ctl_q_info {
enum ice_ctl_q qtype;
- enum ice_aq_err rq_last_status; /* last status on receive queue */
struct ice_ctl_q_ring rq; /* receive queue */
struct ice_ctl_q_ring sq; /* send queue */
u32 sq_cmd_timeout; /* send queue cmd write back timeout */
struct ice_ctl_q_ring rq; /* receive queue */
struct ice_ctl_q_ring sq; /* send queue */
u32 sq_cmd_timeout; /* send queue cmd write back timeout */