-#define GLQDC_DFD_CAM_ACC 0x002D2E24 /* Reset Source: CORER */
-#define GLQDC_DFD_CAM_ACC_CLNUM_S 0
-#define GLQDC_DFD_CAM_ACC_CLNUM_M MAKEMASK(0x7F, 0)
-#define GLQDC_DFD_CAM_ACC_RES_0 0x002D2E28 /* Reset Source: CORER */
-#define GLQDC_DFD_CAM_ACC_RES_0_QID_S 0
-#define GLQDC_DFD_CAM_ACC_RES_0_QID_M MAKEMASK(0x3FFF, 0)
-#define GLQDC_DFD_CAM_ACC_RES_0_CAM_V_S 16
-#define GLQDC_DFD_CAM_ACC_RES_0_CAM_V_M BIT(16)
-#define GLQDC_DFD_CAM_ACC_RES_0_CAM_E_S 31
-#define GLQDC_DFD_CAM_ACC_RES_0_CAM_E_M BIT(31)
-#define GLQDC_DFD_CAM_ACC_RES_1 0x002D2E2C /* Reset Source: CORER */
-#define GLQDC_DFD_CAM_ACC_RES_1_CL_HEAD_S 0
-#define GLQDC_DFD_CAM_ACC_RES_1_CL_HEAD_M MAKEMASK(0x3F, 0)
-#define GLQDC_DFD_CAM_ACC_RES_1_CL_TAIL_S 8
-#define GLQDC_DFD_CAM_ACC_RES_1_CL_TAIL_M MAKEMASK(0x3F, 8)
-#define GLQDC_DFD_CAM_ACC_RES_1_CL_EMPTY_S 16
-#define GLQDC_DFD_CAM_ACC_RES_1_CL_EMPTY_M BIT(16)
-#define GLQDC_DFD_CAM_ACC_RES_1_CL_MALC_S 24
-#define GLQDC_DFD_CAM_ACC_RES_1_CL_MALC_M MAKEMASK(0x3F, 24)
-#define GLQDC_DFD_FIFO_CFG_0 0x002D2E34 /* Reset Source: CORER */
-#define GLQDC_DFD_FIFO_CFG_0_QID_S 0
-#define GLQDC_DFD_FIFO_CFG_0_QID_M MAKEMASK(0x3FFF, 0)
-#define GLQDC_DFD_FIFO_CFG_0_SMPL_PT_S 16
-#define GLQDC_DFD_FIFO_CFG_0_SMPL_PT_M MAKEMASK(0xFF, 16)
-#define GLQDC_DFD_FIFO_CFG_0_ALL_QID_S 31
-#define GLQDC_DFD_FIFO_CFG_0_ALL_QID_M BIT(31)
-#define GLQDC_DFD_FIFO_CFG_1 0x002D2E38 /* Reset Source: CORER */
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_0_S 0
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_0_M MAKEMASK(0x7, 0)
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_1_S 4
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_1_M MAKEMASK(0x7, 4)
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_2_S 8
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_2_M MAKEMASK(0x7, 8)
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_3_S 12
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_3_M MAKEMASK(0x7, 12)
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_4_S 16
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_4_M MAKEMASK(0x7, 16)
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_5_S 20
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_5_M MAKEMASK(0x7, 20)
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_6_S 24
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_6_M MAKEMASK(0x7, 24)
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_7_S 28
-#define GLQDC_DFD_FIFO_CFG_1_PRIO_7_M MAKEMASK(0x7, 28)
-#define GLQDC_DFD_FIFO_SZ_CFG 0x002D30AC /* Reset Source: CORER */
-#define GLQDC_DFD_FIFO_SZ_CFG_COMP_S 0
-#define GLQDC_DFD_FIFO_SZ_CFG_COMP_M MAKEMASK(0xFF, 0)
-#define GLQDC_DFD_FIFO_SZ_CFG_MISS_S 8
-#define GLQDC_DFD_FIFO_SZ_CFG_MISS_M MAKEMASK(0xFF, 8)
-#define GLQDC_DFD_FIFO_SZ_CFG_MISS_COMP_S 16
-#define GLQDC_DFD_FIFO_SZ_CFG_MISS_COMP_M MAKEMASK(0xFF, 16)
-#define GLQDC_DFD_GEN_CHKN 0x002D30A0 /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_CHKN_GEN_BITS_S 0
-#define GLQDC_DFD_GEN_CHKN_GEN_BITS_M MAKEMASK(0xFFFFFFFF, 0)
-#define GLQDC_DFD_GEN_CHKN_2 0x002D30A4 /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_CHKN_2_GEN_BITS_S 0
-#define GLQDC_DFD_GEN_CHKN_2_GEN_BITS_M MAKEMASK(0xFFFFFFFF, 0)
-#define GLQDC_DFD_GEN_CTRL 0x002D2E20 /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_CTRL_ENABLE_S 0
-#define GLQDC_DFD_GEN_CTRL_ENABLE_M BIT(0)
-#define GLQDC_DFD_GEN_CTRL_BLK_INJECT_M1_S 1
-#define GLQDC_DFD_GEN_CTRL_BLK_INJECT_M1_M BIT(1)
-#define GLQDC_DFD_GEN_CTRL_NUM_PAUSE_M1_S 16
-#define GLQDC_DFD_GEN_CTRL_NUM_PAUSE_M1_M MAKEMASK(0x3FF, 16)
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_0 0x002D2EE8 /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_MISS_COMP_ACK_S 0
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_MISS_COMP_ACK_M MAKEMASK(0x7F, 0)
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_MISS_COMP_S 7
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_MISS_COMP_M MAKEMASK(0x7F, 7)
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_COMP_FSM_DATA_S 14
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_COMP_FSM_DATA_M MAKEMASK(0x3, 14)
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_COMP_FSM_S 16
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_COMP_FSM_M MAKEMASK(0x7F, 16)
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_PCIE_OUT_S 23
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_PCIE_OUT_M MAKEMASK(0x7, 23)
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_1 0x002D2EEC /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_1_MISS_FSM_S 0
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_1_MISS_FSM_M MAKEMASK(0x7F, 0)
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_1_DFD_S 7
-#define GLQDC_DFD_GEN_LOG_FIFO_ST_1_DFD_M MAKEMASK(0xFF, 7)
-#define GLQDC_DFD_GEN_LOG_FSM 0x002D2EF0 /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_LOG_FSM_FTSTATE_S 0
-#define GLQDC_DFD_GEN_LOG_FSM_FTSTATE_M MAKEMASK(0x3, 0)
-#define GLQDC_DFD_GEN_LOG_FSM_MISS_FIFO_FSM_ST_S 2
-#define GLQDC_DFD_GEN_LOG_FSM_MISS_FIFO_FSM_ST_M MAKEMASK(0x7, 2)
-#define GLQDC_DFD_GEN_LOG_FSM_IN_MISS_FIFO_S 5
-#define GLQDC_DFD_GEN_LOG_FSM_IN_MISS_FIFO_M MAKEMASK(0x3, 5)
-#define GLQDC_DFD_GEN_LOG_FSM_CPSTATE_S 7
-#define GLQDC_DFD_GEN_LOG_FSM_CPSTATE_M MAKEMASK(0x7, 7)
-#define GLQDC_DFD_GEN_LOGGNG_0 0x002D2EE0 /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_LOGGNG_0_RINGH_WR_RD_S 0
-#define GLQDC_DFD_GEN_LOGGNG_0_RINGH_WR_RD_M BIT(0)
-#define GLQDC_DFD_GEN_LOGGNG_0_QD_WR_RD_S 1
-#define GLQDC_DFD_GEN_LOGGNG_0_QD_WR_RD_M BIT(1)
-#define GLQDC_DFD_GEN_LOGGNG_0_PCIE_RD_REQ_VLD_S 2
-#define GLQDC_DFD_GEN_LOGGNG_0_PCIE_RD_REQ_VLD_M BIT(2)
-#define GLQDC_DFD_GEN_LOGGNG_0_NXT_SQ_VLD_S 3
-#define GLQDC_DFD_GEN_LOGGNG_0_NXT_SQ_VLD_M BIT(3)
-#define GLQDC_DFD_GEN_LOGGNG_0_SQ_VLD_TO_DONE_S 4
-#define GLQDC_DFD_GEN_LOGGNG_0_SQ_VLD_TO_DONE_M BIT(4)
-#define GLQDC_DFD_GEN_LOGGNG_0_PCIE_COMP_VLD_S 5
-#define GLQDC_DFD_GEN_LOGGNG_0_PCIE_COMP_VLD_M BIT(5)
-#define GLQDC_DFD_GEN_LOGGNG_0_FETCH_NXT_SQ_VLD_S 6
-#define GLQDC_DFD_GEN_LOGGNG_0_FETCH_NXT_SQ_VLD_M BIT(6)
-#define GLQDC_DFD_GEN_LOGGNG_0_MALC_RPT_S 8
-#define GLQDC_DFD_GEN_LOGGNG_0_MALC_RPT_M MAKEMASK(0xF, 8)
-#define GLQDC_DFD_GEN_LOGGNG_0_DFD_FIFO_ADD_S 16
-#define GLQDC_DFD_GEN_LOGGNG_0_DFD_FIFO_ADD_M MAKEMASK(0x7F, 16)
-#define GLQDC_DFD_GEN_LOGGNG_1 0x002D2EE4 /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_RFIL_WM_S 0
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_RFIL_WM_M MAKEMASK(0x3, 0)
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_RFIL_S 2
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_RFIL_M MAKEMASK(0x3, 2)
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_MRED_WM_S 4
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_MRED_WM_M MAKEMASK(0x3, 4)
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_MRED_S 6
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_MRED_M MAKEMASK(0x3, 6)
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_M3_WM_S 8
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_M3_WM_M MAKEMASK(0x3, 8)
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_M3_S 10
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_M3_M MAKEMASK(0x3, 10)
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_LSO_MT_M3_WM_S 12
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_LSO_MT_M3_WM_M MAKEMASK(0x3, 12)
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_LSO_MT_M3_S 14
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_LSO_MT_M3_M MAKEMASK(0x3, 14)
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_ACK_MISS_FIFO_M3_WM_S 16
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_ACK_MISS_FIFO_M3_WM_M MAKEMASK(0x3, 16)
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_ACK_MISS_FIFO_M3_S 18
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_ACK_MISS_FIFO_M3_M MAKEMASK(0x3, 18)
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_EVICT_WM_S 20
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_EVICT_WM_M MAKEMASK(0x3, 20)
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_EVICT_S 22
-#define GLQDC_DFD_GEN_LOGGNG_1_WS_EVICT_M MAKEMASK(0x3, 22)
-#define GLQDC_DFD_GEN_LOGGNG_2 0x002D2FFC /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_LOGGNG_2_WR_WHEN_FULL_S 0
-#define GLQDC_DFD_GEN_LOGGNG_2_WR_WHEN_FULL_M MAKEMASK(0x3F, 0)
-#define GLQDC_DFD_GEN_LOGGNG_2_WR_WHEN_FULL_LT_S 6
-#define GLQDC_DFD_GEN_LOGGNG_2_WR_WHEN_FULL_LT_M MAKEMASK(0x3F, 6)
-#define GLQDC_DFD_GEN_LOGGNG_2_TEST_S 24
-#define GLQDC_DFD_GEN_LOGGNG_2_TEST_M MAKEMASK(0xFF, 24)
-#define GLQDC_DFD_GEN_LOGGNG_3 0x002D3008 /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_LOGGNG_3_GEN_S 0
-#define GLQDC_DFD_GEN_LOGGNG_3_GEN_M MAKEMASK(0xFFFFFFFF, 0)
-#define GLQDC_DFD_GEN_LOGGNG_4 0x002D300C /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_LOGGNG_4_GEN_S 0
-#define GLQDC_DFD_GEN_LOGGNG_4_GEN_M MAKEMASK(0xFFFFFFFF, 0)
-#define GLQDC_DFD_GEN_LOGGNG_5 0x002D3010 /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_LOGGNG_5_GEN_S 0
-#define GLQDC_DFD_GEN_LOGGNG_5_GEN_M MAKEMASK(0xFFFFFFFF, 0)
-#define GLQDC_DFD_GEN_LOGGNG_6 0x002D3014 /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_LOGGNG_6_GEN_S 0
-#define GLQDC_DFD_GEN_LOGGNG_6_GEN_M MAKEMASK(0xFFFFFFFF, 0)
-#define GLQDC_DFD_GEN_STAT_REGS(_i) (0x002D3018 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
-#define GLQDC_DFD_GEN_STAT_REGS_MAX_INDEX 15
-#define GLQDC_DFD_GEN_STAT_REGS_COUNT_S 0
-#define GLQDC_DFD_GEN_STAT_REGS_COUNT_M MAKEMASK(0xFFFFFFFF, 0)
-#define GLQDC_DFD_LOG_0 0x002D2E3C /* Reset Source: CORER */
-#define GLQDC_DFD_LOG_0_SOURCE_S 0
-#define GLQDC_DFD_LOG_0_SOURCE_M MAKEMASK(0x3, 0)
-#define GLQDC_DFD_LOG_0_LVL_OR_EDGE_S 4
-#define GLQDC_DFD_LOG_0_LVL_OR_EDGE_M BIT(4)
-#define GLQDC_DFD_LOG_0_DLY_CYCL_S 16
-#define GLQDC_DFD_LOG_0_DLY_CYCL_M MAKEMASK(0x3FF, 16)
-#define GLQDC_DFD_LOG_1 0x002D2E40 /* Reset Source: CORER */
-#define GLQDC_DFD_LOG_1_NUM_EVENTS_S 0
-#define GLQDC_DFD_LOG_1_NUM_EVENTS_M MAKEMASK(0x3FF, 0)
-#define GLQDC_DFD_LOG_1_NUM_TRIGS_S 16
-#define GLQDC_DFD_LOG_1_NUM_TRIGS_M MAKEMASK(0x3FF, 16)
-#define GLQDC_DFD_LOG_1_TRIG_B2B_S 31
-#define GLQDC_DFD_LOG_1_TRIG_B2B_M BIT(31)
-#define GLQDC_DFD_LOG_ACTN_EN 0x002D2EA4 /* Reset Source: CORER */
-#define GLQDC_DFD_LOG_ACTN_EN_BLK_INJECT_M1_S 0
-#define GLQDC_DFD_LOG_ACTN_EN_BLK_INJECT_M1_M BIT(0)
-#define GLQDC_DFD_LOG_ACTN_EN_STP_WR_DFD_FIFO_S 1
-#define GLQDC_DFD_LOG_ACTN_EN_STP_WR_DFD_FIFO_M BIT(1)
-#define GLQDC_DFD_LOG_ACTN_EN_STP_UPDT_MALC_RPT_CSR_S 2
-#define GLQDC_DFD_LOG_ACTN_EN_STP_UPDT_MALC_RPT_CSR_M BIT(2)
-#define GLQDC_DFD_LOG_ACTN_RST 0x002D2EA8 /* Reset Source: CORER */
-#define GLQDC_DFD_LOG_ACTN_RST_BLK_INJECT_M1_S 0
-#define GLQDC_DFD_LOG_ACTN_RST_BLK_INJECT_M1_M BIT(0)
-#define GLQDC_DFD_LOG_ACTN_RST_STP_WR_DFD_FIFO_S 1
-#define GLQDC_DFD_LOG_ACTN_RST_STP_WR_DFD_FIFO_M BIT(1)
-#define GLQDC_DFD_LOG_ACTN_RST_STP_UPDT_MALC_RPT_CSR_S 2
-#define GLQDC_DFD_LOG_ACTN_RST_STP_UPDT_MALC_RPT_CSR_M BIT(2)
-#define GLQDC_DFD_LOG_DATA(_i) (0x002D2E44 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: CORER */
-#define GLQDC_DFD_LOG_DATA_MAX_INDEX 11
-#define GLQDC_DFD_LOG_DATA_DATA_S 0
-#define GLQDC_DFD_LOG_DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
-#define GLQDC_DFD_LOG_MASK(_i) (0x002D2E74 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: CORER */
-#define GLQDC_DFD_LOG_MASK_MAX_INDEX 11
-#define GLQDC_DFD_LOG_MASK_MASK_S 0
-#define GLQDC_DFD_LOG_MASK_MASK_M MAKEMASK(0xFFFFFFFF, 0)
-#define GLQDC_DFD_LOG_TRG_0 0x002D2EAC /* Reset Source: CORER */
-#define GLQDC_DFD_LOG_TRG_0_QID_S 0
-#define GLQDC_DFD_LOG_TRG_0_QID_M MAKEMASK(0x3FFF, 0)
-#define GLQDC_DFD_LOG_TRG_0_ACT_TRIGGED_S 16
-#define GLQDC_DFD_LOG_TRG_0_ACT_TRIGGED_M BIT(16)
-#define GLQDC_DFD_LOG_TRG_0_TRIGGED_S 31
-#define GLQDC_DFD_LOG_TRG_0_TRIGGED_M BIT(31)
-#define GLQDC_DFD_LOG_TRG_DATA(_i) (0x002D2EB0 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: CORER */
-#define GLQDC_DFD_LOG_TRG_DATA_MAX_INDEX 11
-#define GLQDC_DFD_LOG_TRG_DATA_DATA_S 0
-#define GLQDC_DFD_LOG_TRG_DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
-#define GLQDC_DFD_PACE 0x002D3000 /* Reset Source: CORER */
-#define GLQDC_DFD_PACE_PUSH_S 0
-#define GLQDC_DFD_PACE_PUSH_M BIT(0)
-#define GLQDC_DFD_RST 0x002D2E30 /* Reset Source: CORER */
-#define GLQDC_DFD_RST_RST_S 0
-#define GLQDC_DFD_RST_RST_M BIT(0)
-#define GLQDC_DFD_RST_CLR_MALC_RPT_S 1
-#define GLQDC_DFD_RST_CLR_MALC_RPT_M BIT(1)
-#define GLQDC_DFD_RST_LOG_RST_S 2
-#define GLQDC_DFD_RST_LOG_RST_M BIT(2)
-#define GLQDC_DFD_SAMPLE_RO_CSR 0x002D3004 /* Reset Source: CORER */
-#define GLQDC_DFD_SAMPLE_RO_CSR_SMPL_S 0
-#define GLQDC_DFD_SAMPLE_RO_CSR_SMPL_M BIT(0)
-#define GLQDC_DFD_STATS_CFG_0 0x002D3058 /* Reset Source: CORER */
-#define GLQDC_DFD_STATS_CFG_0_CLR_S 0
-#define GLQDC_DFD_STATS_CFG_0_CLR_M BIT(0)
-#define GLQDC_DFD_STATS_CFG_1 0x002D305C /* Reset Source: CORER */
-#define GLQDC_DFD_STATS_CFG_1_QID_S 0
-#define GLQDC_DFD_STATS_CFG_1_QID_M MAKEMASK(0x3FFF, 0)
-#define GLQDC_DFD_STATS_CFG_1_GEN_CFG_S 16
-#define GLQDC_DFD_STATS_CFG_1_GEN_CFG_M MAKEMASK(0x1F, 16)
-#define GLQDC_DFD_STATS_CFG_EVNT(_i) (0x002D3060 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
-#define GLQDC_DFD_STATS_CFG_EVNT_MAX_INDEX 15
-#define GLQDC_DFD_STATS_CFG_EVNT_EVNT_ID_S 0
-#define GLQDC_DFD_STATS_CFG_EVNT_EVNT_ID_M MAKEMASK(0x1F, 0)
-#define GLQDC_DFD_STATS_CFG_EVNT_WRAP_EN_S 31
-#define GLQDC_DFD_STATS_CFG_EVNT_WRAP_EN_M BIT(31)
-#define GLQDC_DFD_TEST_MNG 0x002D30A8 /* Reset Source: CORER */
-#define GLQDC_DFD_TEST_MNG_TST_S 2
-#define GLQDC_DFD_TEST_MNG_TST_M BIT(2)