+#define IGC_HKEY_MAX_INDEX 10
+#define IGC_RSS_RDT_SIZD 128
+
+#define IGC_DEFAULT_REG_SIZE 4
+#define IGC_DEFAULT_REG_SIZE_MASK 0xf
+
+#define IGC_RSS_RDT_REG_SIZE IGC_DEFAULT_REG_SIZE
+#define IGC_RSS_RDT_REG_SIZE_MASK IGC_DEFAULT_REG_SIZE_MASK
+#define IGC_HKEY_REG_SIZE IGC_DEFAULT_REG_SIZE
+#define IGC_HKEY_SIZE (IGC_HKEY_REG_SIZE * IGC_HKEY_MAX_INDEX)
+
+/*
+ * The overhead from MTU to max frame size.
+ * Considering VLAN so tag needs to be counted.
+ */
+#define IGC_ETH_OVERHEAD (RTE_ETHER_HDR_LEN + \
+ RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2)
+
+/*
+ * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
+ * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary.
+ * This will also optimize cache line size effect.
+ * H/W supports up to cache line size 128.
+ */
+#define IGC_ALIGN 128
+
+#define IGC_TX_DESCRIPTOR_MULTIPLE 8
+#define IGC_RX_DESCRIPTOR_MULTIPLE 8
+
+#define IGC_RXD_ALIGN ((uint16_t)(IGC_ALIGN / \
+ sizeof(union igc_adv_rx_desc)))
+#define IGC_TXD_ALIGN ((uint16_t)(IGC_ALIGN / \
+ sizeof(union igc_adv_tx_desc)))
+#define IGC_MIN_TXD IGC_TX_DESCRIPTOR_MULTIPLE
+#define IGC_MAX_TXD ((uint16_t)(0x80000 / sizeof(union igc_adv_tx_desc)))
+#define IGC_MIN_RXD IGC_RX_DESCRIPTOR_MULTIPLE
+#define IGC_MAX_RXD ((uint16_t)(0x80000 / sizeof(union igc_adv_rx_desc)))
+
+#define IGC_TX_MAX_SEG UINT8_MAX
+#define IGC_TX_MAX_MTU_SEG UINT8_MAX
+
+#define IGC_RX_OFFLOAD_ALL ( \
+ RTE_ETH_RX_OFFLOAD_VLAN_STRIP | \
+ RTE_ETH_RX_OFFLOAD_VLAN_FILTER | \
+ RTE_ETH_RX_OFFLOAD_VLAN_EXTEND | \
+ RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | \
+ RTE_ETH_RX_OFFLOAD_UDP_CKSUM | \
+ RTE_ETH_RX_OFFLOAD_TCP_CKSUM | \
+ RTE_ETH_RX_OFFLOAD_SCTP_CKSUM | \
+ RTE_ETH_RX_OFFLOAD_KEEP_CRC | \
+ RTE_ETH_RX_OFFLOAD_SCATTER | \
+ RTE_ETH_RX_OFFLOAD_RSS_HASH)
+
+#define IGC_TX_OFFLOAD_ALL ( \
+ RTE_ETH_TX_OFFLOAD_VLAN_INSERT | \
+ RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | \
+ RTE_ETH_TX_OFFLOAD_UDP_CKSUM | \
+ RTE_ETH_TX_OFFLOAD_TCP_CKSUM | \
+ RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | \
+ RTE_ETH_TX_OFFLOAD_TCP_TSO | \
+ RTE_ETH_TX_OFFLOAD_UDP_TSO | \
+ RTE_ETH_TX_OFFLOAD_MULTI_SEGS)
+
+#define IGC_RSS_OFFLOAD_ALL ( \
+ RTE_ETH_RSS_IPV4 | \
+ RTE_ETH_RSS_NONFRAG_IPV4_TCP | \
+ RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
+ RTE_ETH_RSS_IPV6 | \
+ RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
+ RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
+ RTE_ETH_RSS_IPV6_EX | \
+ RTE_ETH_RSS_IPV6_TCP_EX | \
+ RTE_ETH_RSS_IPV6_UDP_EX)
+
+#define IGC_MAX_ETQF_FILTERS 3 /* etqf(3) is used for 1588 */
+#define IGC_ETQF_FILTER_1588 3
+#define IGC_ETQF_QUEUE_SHIFT 16
+#define IGC_ETQF_QUEUE_MASK (7u << IGC_ETQF_QUEUE_SHIFT)
+
+#define IGC_MAX_NTUPLE_FILTERS 8
+#define IGC_NTUPLE_MAX_PRI 7
+
+#define IGC_SYN_FILTER_ENABLE 0x01 /* syn filter enable field */
+#define IGC_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field */
+#define IGC_SYN_FILTER_QUEUE 0x0000000E /* syn filter queue field */
+#define IGC_RFCTL_SYNQFP 0x00080000 /* SYNQFP in RFCTL register */
+