+#include "ionic.h"
+#include "ionic_dev.h"
+#include "ionic_mac_api.h"
+#include "ionic_lif.h"
+#include "ionic_ethdev.h"
+#include "ionic_rxtx.h"
+
+static int eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
+static int eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev);
+static int ionic_dev_info_get(struct rte_eth_dev *eth_dev,
+ struct rte_eth_dev_info *dev_info);
+static int ionic_dev_configure(struct rte_eth_dev *dev);
+static int ionic_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
+static int ionic_dev_start(struct rte_eth_dev *dev);
+static int ionic_dev_stop(struct rte_eth_dev *dev);
+static int ionic_dev_close(struct rte_eth_dev *dev);
+static int ionic_dev_set_link_up(struct rte_eth_dev *dev);
+static int ionic_dev_set_link_down(struct rte_eth_dev *dev);
+static int ionic_dev_link_update(struct rte_eth_dev *eth_dev,
+ int wait_to_complete);
+static int ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev,
+ struct rte_eth_fc_conf *fc_conf);
+static int ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev,
+ struct rte_eth_fc_conf *fc_conf);
+static int ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask);
+static int ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev,
+ struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size);
+static int ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev,
+ struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size);
+static int ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
+ struct rte_eth_rss_conf *rss_conf);
+static int ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev,
+ struct rte_eth_rss_conf *rss_conf);
+static int ionic_dev_stats_get(struct rte_eth_dev *eth_dev,
+ struct rte_eth_stats *stats);
+static int ionic_dev_stats_reset(struct rte_eth_dev *eth_dev);
+static int ionic_dev_xstats_get(struct rte_eth_dev *dev,
+ struct rte_eth_xstat *xstats, unsigned int n);
+static int ionic_dev_xstats_get_by_id(struct rte_eth_dev *dev,
+ const uint64_t *ids, uint64_t *values, unsigned int n);
+static int ionic_dev_xstats_reset(struct rte_eth_dev *dev);
+static int ionic_dev_xstats_get_names(struct rte_eth_dev *dev,
+ struct rte_eth_xstat_name *xstats_names, unsigned int size);
+static int ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
+ struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
+ unsigned int limit);
+static int ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev,
+ char *fw_version, size_t fw_size);
+
+static const struct rte_pci_id pci_id_ionic_map[] = {
+ { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_PF) },
+ { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_VF) },
+ { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_MGMT) },
+ { .vendor_id = 0, /* sentinel */ },
+};
+
+static const struct rte_eth_desc_lim rx_desc_lim = {
+ .nb_max = IONIC_MAX_RING_DESC,
+ .nb_min = IONIC_MIN_RING_DESC,
+ .nb_align = 1,
+};
+
+static const struct rte_eth_desc_lim tx_desc_lim = {
+ .nb_max = IONIC_MAX_RING_DESC,
+ .nb_min = IONIC_MIN_RING_DESC,
+ .nb_align = 1,
+ .nb_seg_max = IONIC_TX_MAX_SG_ELEMS,
+ .nb_mtu_seg_max = IONIC_TX_MAX_SG_ELEMS,
+};
+
+static const struct eth_dev_ops ionic_eth_dev_ops = {
+ .dev_infos_get = ionic_dev_info_get,
+ .dev_configure = ionic_dev_configure,
+ .mtu_set = ionic_dev_mtu_set,
+ .dev_start = ionic_dev_start,
+ .dev_stop = ionic_dev_stop,
+ .dev_close = ionic_dev_close,
+ .link_update = ionic_dev_link_update,
+ .dev_set_link_up = ionic_dev_set_link_up,
+ .dev_set_link_down = ionic_dev_set_link_down,
+ .mac_addr_add = ionic_dev_add_mac,
+ .mac_addr_remove = ionic_dev_remove_mac,
+ .mac_addr_set = ionic_dev_set_mac,
+ .vlan_filter_set = ionic_dev_vlan_filter_set,
+ .promiscuous_enable = ionic_dev_promiscuous_enable,
+ .promiscuous_disable = ionic_dev_promiscuous_disable,
+ .allmulticast_enable = ionic_dev_allmulticast_enable,
+ .allmulticast_disable = ionic_dev_allmulticast_disable,
+ .flow_ctrl_get = ionic_flow_ctrl_get,
+ .flow_ctrl_set = ionic_flow_ctrl_set,
+ .rxq_info_get = ionic_rxq_info_get,
+ .txq_info_get = ionic_txq_info_get,
+ .rx_queue_setup = ionic_dev_rx_queue_setup,
+ .rx_queue_release = ionic_dev_rx_queue_release,
+ .rx_queue_start = ionic_dev_rx_queue_start,
+ .rx_queue_stop = ionic_dev_rx_queue_stop,
+ .tx_queue_setup = ionic_dev_tx_queue_setup,
+ .tx_queue_release = ionic_dev_tx_queue_release,
+ .tx_queue_start = ionic_dev_tx_queue_start,
+ .tx_queue_stop = ionic_dev_tx_queue_stop,
+ .vlan_offload_set = ionic_vlan_offload_set,
+ .reta_update = ionic_dev_rss_reta_update,
+ .reta_query = ionic_dev_rss_reta_query,
+ .rss_hash_conf_get = ionic_dev_rss_hash_conf_get,
+ .rss_hash_update = ionic_dev_rss_hash_update,
+ .stats_get = ionic_dev_stats_get,
+ .stats_reset = ionic_dev_stats_reset,
+ .xstats_get = ionic_dev_xstats_get,
+ .xstats_get_by_id = ionic_dev_xstats_get_by_id,
+ .xstats_reset = ionic_dev_xstats_reset,
+ .xstats_get_names = ionic_dev_xstats_get_names,
+ .xstats_get_names_by_id = ionic_dev_xstats_get_names_by_id,
+ .fw_version_get = ionic_dev_fw_version_get,
+};
+
+struct rte_ionic_xstats_name_off {
+ char name[RTE_ETH_XSTATS_NAME_SIZE];
+ unsigned int offset;
+};
+
+static const struct rte_ionic_xstats_name_off rte_ionic_xstats_strings[] = {
+ /* RX */
+ {"rx_ucast_bytes", offsetof(struct ionic_lif_stats,
+ rx_ucast_bytes)},
+ {"rx_ucast_packets", offsetof(struct ionic_lif_stats,
+ rx_ucast_packets)},
+ {"rx_mcast_bytes", offsetof(struct ionic_lif_stats,
+ rx_mcast_bytes)},
+ {"rx_mcast_packets", offsetof(struct ionic_lif_stats,
+ rx_mcast_packets)},
+ {"rx_bcast_bytes", offsetof(struct ionic_lif_stats,
+ rx_bcast_bytes)},
+ {"rx_bcast_packets", offsetof(struct ionic_lif_stats,
+ rx_bcast_packets)},
+ /* RX drops */
+ {"rx_ucast_drop_bytes", offsetof(struct ionic_lif_stats,
+ rx_ucast_drop_bytes)},
+ {"rx_ucast_drop_packets", offsetof(struct ionic_lif_stats,
+ rx_ucast_drop_packets)},
+ {"rx_mcast_drop_bytes", offsetof(struct ionic_lif_stats,
+ rx_mcast_drop_bytes)},
+ {"rx_mcast_drop_packets", offsetof(struct ionic_lif_stats,
+ rx_mcast_drop_packets)},
+ {"rx_bcast_drop_bytes", offsetof(struct ionic_lif_stats,
+ rx_bcast_drop_bytes)},
+ {"rx_bcast_drop_packets", offsetof(struct ionic_lif_stats,
+ rx_bcast_drop_packets)},
+ {"rx_dma_error", offsetof(struct ionic_lif_stats,
+ rx_dma_error)},
+ /* TX */
+ {"tx_ucast_bytes", offsetof(struct ionic_lif_stats,
+ tx_ucast_bytes)},
+ {"tx_ucast_packets", offsetof(struct ionic_lif_stats,
+ tx_ucast_packets)},
+ {"tx_mcast_bytes", offsetof(struct ionic_lif_stats,
+ tx_mcast_bytes)},
+ {"tx_mcast_packets", offsetof(struct ionic_lif_stats,
+ tx_mcast_packets)},
+ {"tx_bcast_bytes", offsetof(struct ionic_lif_stats,
+ tx_bcast_bytes)},
+ {"tx_bcast_packets", offsetof(struct ionic_lif_stats,
+ tx_bcast_packets)},
+ /* TX drops */
+ {"tx_ucast_drop_bytes", offsetof(struct ionic_lif_stats,
+ tx_ucast_drop_bytes)},
+ {"tx_ucast_drop_packets", offsetof(struct ionic_lif_stats,
+ tx_ucast_drop_packets)},
+ {"tx_mcast_drop_bytes", offsetof(struct ionic_lif_stats,
+ tx_mcast_drop_bytes)},
+ {"tx_mcast_drop_packets", offsetof(struct ionic_lif_stats,
+ tx_mcast_drop_packets)},
+ {"tx_bcast_drop_bytes", offsetof(struct ionic_lif_stats,
+ tx_bcast_drop_bytes)},
+ {"tx_bcast_drop_packets", offsetof(struct ionic_lif_stats,
+ tx_bcast_drop_packets)},
+ {"tx_dma_error", offsetof(struct ionic_lif_stats,
+ tx_dma_error)},
+ /* Rx Queue/Ring drops */
+ {"rx_queue_disabled", offsetof(struct ionic_lif_stats,
+ rx_queue_disabled)},
+ {"rx_queue_empty", offsetof(struct ionic_lif_stats,
+ rx_queue_empty)},
+ {"rx_queue_error", offsetof(struct ionic_lif_stats,
+ rx_queue_error)},
+ {"rx_desc_fetch_error", offsetof(struct ionic_lif_stats,
+ rx_desc_fetch_error)},
+ {"rx_desc_data_error", offsetof(struct ionic_lif_stats,
+ rx_desc_data_error)},
+ /* Tx Queue/Ring drops */
+ {"tx_queue_disabled", offsetof(struct ionic_lif_stats,
+ tx_queue_disabled)},
+ {"tx_queue_error", offsetof(struct ionic_lif_stats,
+ tx_queue_error)},
+ {"tx_desc_fetch_error", offsetof(struct ionic_lif_stats,
+ tx_desc_fetch_error)},
+ {"tx_desc_data_error", offsetof(struct ionic_lif_stats,
+ tx_desc_data_error)},
+};
+
+#define IONIC_NB_HW_STATS (sizeof(rte_ionic_xstats_strings) / \
+ sizeof(rte_ionic_xstats_strings[0]))
+
+static int
+ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev,
+ char *fw_version, size_t fw_size)
+{
+ struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
+ struct ionic_adapter *adapter = lif->adapter;
+
+ if (fw_version == NULL || fw_size <= 0)
+ return -EINVAL;
+
+ snprintf(fw_version, fw_size, "%s",
+ adapter->fw_version);
+ fw_version[fw_size - 1] = '\0';
+
+ return 0;
+}
+
+/*
+ * Set device link up, enable tx.
+ */
+static int
+ionic_dev_set_link_up(struct rte_eth_dev *eth_dev)
+{
+ struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
+ struct ionic_adapter *adapter = lif->adapter;
+ struct ionic_dev *idev = &adapter->idev;
+ int err;
+
+ IONIC_PRINT_CALL();
+
+ ionic_dev_cmd_port_state(idev, IONIC_PORT_ADMIN_STATE_UP);
+
+ err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
+ if (err) {
+ IONIC_PRINT(WARNING, "Failed to bring port UP");
+ return err;
+ }
+
+ return 0;
+}
+
+/*
+ * Set device link down, disable tx.
+ */
+static int
+ionic_dev_set_link_down(struct rte_eth_dev *eth_dev)
+{
+ struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
+ struct ionic_adapter *adapter = lif->adapter;
+ struct ionic_dev *idev = &adapter->idev;
+ int err;
+
+ IONIC_PRINT_CALL();
+
+ ionic_dev_cmd_port_state(idev, IONIC_PORT_ADMIN_STATE_DOWN);
+
+ err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
+ if (err) {
+ IONIC_PRINT(WARNING, "Failed to bring port DOWN");
+ return err;
+ }
+
+ return 0;
+}
+
+static int
+ionic_dev_link_update(struct rte_eth_dev *eth_dev,
+ int wait_to_complete __rte_unused)
+{
+ struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
+ struct ionic_adapter *adapter = lif->adapter;
+ struct rte_eth_link link;
+
+ IONIC_PRINT_CALL();
+
+ /* Initialize */
+ memset(&link, 0, sizeof(link));
+ link.link_autoneg = ETH_LINK_AUTONEG;
+
+ if (!adapter->link_up) {
+ /* Interface is down */
+ link.link_status = ETH_LINK_DOWN;
+ link.link_duplex = ETH_LINK_HALF_DUPLEX;
+ link.link_speed = ETH_SPEED_NUM_NONE;
+ } else {
+ /* Interface is up */
+ link.link_status = ETH_LINK_UP;
+ link.link_duplex = ETH_LINK_FULL_DUPLEX;
+ switch (adapter->link_speed) {
+ case 10000:
+ link.link_speed = ETH_SPEED_NUM_10G;
+ break;
+ case 25000:
+ link.link_speed = ETH_SPEED_NUM_25G;
+ break;
+ case 40000:
+ link.link_speed = ETH_SPEED_NUM_40G;
+ break;
+ case 50000:
+ link.link_speed = ETH_SPEED_NUM_50G;
+ break;
+ case 100000:
+ link.link_speed = ETH_SPEED_NUM_100G;
+ break;
+ default:
+ link.link_speed = ETH_SPEED_NUM_NONE;
+ break;
+ }
+ }
+
+ return rte_eth_linkstatus_set(eth_dev, &link);
+}
+
+/**
+ * Interrupt handler triggered by NIC for handling
+ * specific interrupt.
+ *
+ * @param param
+ * The address of parameter registered before.
+ *
+ * @return
+ * void
+ */
+static void
+ionic_dev_interrupt_handler(void *param)
+{
+ struct ionic_adapter *adapter = (struct ionic_adapter *)param;
+ uint32_t i;
+
+ IONIC_PRINT(DEBUG, "->");
+
+ for (i = 0; i < adapter->nlifs; i++) {
+ if (adapter->lifs[i])
+ ionic_notifyq_handler(adapter->lifs[i], -1);
+ }
+}
+
+static int
+ionic_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
+{
+ struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
+ uint32_t max_frame_size;
+ int err;
+
+ IONIC_PRINT_CALL();
+
+ /*
+ * Note: mtu check against IONIC_MIN_MTU, IONIC_MAX_MTU
+ * is done by the the API.
+ */
+
+ /*
+ * Max frame size is MTU + Ethernet header + VLAN + QinQ
+ * (plus ETHER_CRC_LEN if the adapter is able to keep CRC)
+ */
+ max_frame_size = mtu + RTE_ETHER_HDR_LEN + 4 + 4;
+
+ if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len < max_frame_size)
+ return -EINVAL;
+
+ err = ionic_lif_change_mtu(lif, mtu);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static int
+ionic_dev_info_get(struct rte_eth_dev *eth_dev,
+ struct rte_eth_dev_info *dev_info)
+{
+ struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
+ struct ionic_adapter *adapter = lif->adapter;
+ struct ionic_identity *ident = &adapter->ident;
+
+ IONIC_PRINT_CALL();
+
+ dev_info->max_rx_queues = (uint16_t)
+ ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ];
+ dev_info->max_tx_queues = (uint16_t)
+ ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ];
+ /* Also add ETHER_CRC_LEN if the adapter is able to keep CRC */
+ dev_info->min_rx_bufsize = IONIC_MIN_MTU + RTE_ETHER_HDR_LEN;
+ dev_info->max_rx_pktlen = IONIC_MAX_MTU + RTE_ETHER_HDR_LEN;
+ dev_info->max_mac_addrs = adapter->max_mac_addrs;
+ dev_info->min_mtu = IONIC_MIN_MTU;
+ dev_info->max_mtu = IONIC_MAX_MTU;
+
+ dev_info->hash_key_size = IONIC_RSS_HASH_KEY_SIZE;
+ dev_info->reta_size = ident->lif.eth.rss_ind_tbl_sz;
+ dev_info->flow_type_rss_offloads = IONIC_ETH_RSS_OFFLOAD_ALL;
+
+ dev_info->speed_capa =
+ ETH_LINK_SPEED_10G |
+ ETH_LINK_SPEED_25G |
+ ETH_LINK_SPEED_40G |
+ ETH_LINK_SPEED_50G |
+ ETH_LINK_SPEED_100G;
+
+ /*
+ * Per-queue capabilities. Actually most of the offloads are enabled
+ * by default on the port and can be used on selected queues (by adding
+ * packet flags at runtime when required)
+ */
+
+ dev_info->rx_queue_offload_capa =
+ DEV_RX_OFFLOAD_IPV4_CKSUM |
+ DEV_RX_OFFLOAD_UDP_CKSUM |
+ DEV_RX_OFFLOAD_TCP_CKSUM |
+ 0;
+
+ dev_info->tx_queue_offload_capa =
+ DEV_TX_OFFLOAD_IPV4_CKSUM |
+ DEV_TX_OFFLOAD_UDP_CKSUM |
+ DEV_TX_OFFLOAD_TCP_CKSUM |
+ DEV_TX_OFFLOAD_VLAN_INSERT |
+ DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
+ DEV_TX_OFFLOAD_OUTER_UDP_CKSUM |
+ 0;
+
+ /*
+ * Per-port capabilities
+ * See ionic_set_features to request and check supported features
+ */
+
+ dev_info->rx_offload_capa = dev_info->rx_queue_offload_capa |
+ DEV_RX_OFFLOAD_JUMBO_FRAME |
+ DEV_RX_OFFLOAD_VLAN_FILTER |
+ DEV_RX_OFFLOAD_VLAN_STRIP |
+ DEV_RX_OFFLOAD_SCATTER |
+ 0;
+
+ dev_info->tx_offload_capa = dev_info->tx_queue_offload_capa |
+ DEV_TX_OFFLOAD_MULTI_SEGS |
+ DEV_TX_OFFLOAD_TCP_TSO |
+ 0;
+
+ dev_info->rx_desc_lim = rx_desc_lim;
+ dev_info->tx_desc_lim = tx_desc_lim;
+
+ /* Driver-preferred Rx/Tx parameters */
+ dev_info->default_rxportconf.burst_size = 32;
+ dev_info->default_txportconf.burst_size = 32;
+ dev_info->default_rxportconf.nb_queues = 1;
+ dev_info->default_txportconf.nb_queues = 1;
+ dev_info->default_rxportconf.ring_size = IONIC_DEF_TXRX_DESC;
+ dev_info->default_txportconf.ring_size = IONIC_DEF_TXRX_DESC;
+
+ return 0;
+}
+
+static int
+ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev,
+ struct rte_eth_fc_conf *fc_conf)
+{
+ struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
+ struct ionic_adapter *adapter = lif->adapter;
+ struct ionic_dev *idev = &adapter->idev;
+
+ if (idev->port_info) {
+ fc_conf->autoneg = idev->port_info->config.an_enable;