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net/ixgbe: check security enable bits
[dpdk.git]
/
drivers
/
net
/
ixgbe
/
base
/
ixgbe_osdep.h
diff --git
a/drivers/net/ixgbe/base/ixgbe_osdep.h
b/drivers/net/ixgbe/base/ixgbe_osdep.h
index
fe532aa
..
bb5dfd2
100644
(file)
--- a/
drivers/net/ixgbe/base/ixgbe_osdep.h
+++ b/
drivers/net/ixgbe/base/ixgbe_osdep.h
@@
-44,6
+44,7
@@
#include <rte_cycles.h>
#include <rte_log.h>
#include <rte_byteorder.h>
#include <rte_cycles.h>
#include <rte_log.h>
#include <rte_byteorder.h>
+#include <rte_io.h>
#include "../ixgbe_logs.h"
#include "../ixgbe_bypass_defines.h"
#include "../ixgbe_logs.h"
#include "../ixgbe_bypass_defines.h"
@@
-123,16
+124,18
@@
typedef int bool;
#define prefetch(x) rte_prefetch0(x)
#define prefetch(x) rte_prefetch0(x)
-#define IXGBE_PCI_REG(reg)
(*((volatile uint32_t *)(reg))
)
+#define IXGBE_PCI_REG(reg)
rte_read32(reg
)
static inline uint32_t ixgbe_read_addr(volatile void* addr)
{
return rte_le_to_cpu_32(IXGBE_PCI_REG(addr));
}
static inline uint32_t ixgbe_read_addr(volatile void* addr)
{
return rte_le_to_cpu_32(IXGBE_PCI_REG(addr));
}
-#define IXGBE_PCI_REG_WRITE(reg, value) do { \
- IXGBE_PCI_REG((reg)) = (rte_cpu_to_le_32(value)); \
-} while(0)
+#define IXGBE_PCI_REG_WRITE(reg, value) \
+ rte_write32((rte_cpu_to_le_32(value)), reg)
+
+#define IXGBE_PCI_REG_WRITE_RELAXED(reg, value) \
+ rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
#define IXGBE_PCI_REG_ADDR(hw, reg) \
((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))
#define IXGBE_PCI_REG_ADDR(hw, reg) \
((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))
@@
-158,4
+161,12
@@
static inline uint32_t ixgbe_read_addr(volatile void* addr)
#define IXGBE_WRITE_REG_ARRAY(hw, reg, index, value) \
IXGBE_PCI_REG_WRITE(IXGBE_PCI_REG_ARRAY_ADDR((hw), (reg), (index)), (value))
#define IXGBE_WRITE_REG_ARRAY(hw, reg, index, value) \
IXGBE_PCI_REG_WRITE(IXGBE_PCI_REG_ARRAY_ADDR((hw), (reg), (index)), (value))
+#define IXGBE_WRITE_REG_THEN_POLL_MASK(hw, reg, val, mask, poll_ms) \
+do { \
+ uint32_t cnt = poll_ms; \
+ IXGBE_WRITE_REG(hw, (reg), (val)); \
+ while (((IXGBE_READ_REG(hw, (reg))) & (mask)) && (cnt--)) \
+ rte_delay_ms(1); \
+} while (0)
+
#endif /* _IXGBE_OS_H_ */
#endif /* _IXGBE_OS_H_ */