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net/qede/base: fix macros to check chip revision/metal
[dpdk.git]
/
drivers
/
net
/
ixgbe
/
ixgbe_bypass.c
diff --git
a/drivers/net/ixgbe/ixgbe_bypass.c
b/drivers/net/ixgbe/ixgbe_bypass.c
index
e846946
..
38a4493
100644
(file)
--- a/
drivers/net/ixgbe/ixgbe_bypass.c
+++ b/
drivers/net/ixgbe/ixgbe_bypass.c
@@
-36,6
+36,7
@@
#include <rte_ethdev.h>
#include "ixgbe_ethdev.h"
#include "ixgbe_bypass_api.h"
#include <rte_ethdev.h>
#include "ixgbe_ethdev.h"
#include "ixgbe_bypass_api.h"
+#include "rte_pmd_ixgbe.h"
#define BYPASS_STATUS_OFF_MASK 3
#define BYPASS_STATUS_OFF_MASK 3
@@
-46,7
+47,7
@@
__func__, __LINE__); \
return retval; \
} \
__func__, __LINE__); \
return retval; \
} \
-} while(0)
+} while
(0)
#define FUNC_PTR_OR_RET(func) do { \
if ((func) == NULL) { \
#define FUNC_PTR_OR_RET(func) do { \
if ((func) == NULL) { \
@@
-54,7
+55,7
@@
__func__, __LINE__); \
return; \
} \
__func__, __LINE__); \
return; \
} \
-} while(0)
+} while
(0)
/**
/**
@@
-82,7
+83,7
@@
ixgbe_bypass_set_time(struct ixgbe_adapter *adapter)
BYPASS_CTL1_VALID_M |
BYPASS_CTL1_OFFTRST_M;
value = (sec & BYPASS_CTL1_TIME_M) |
BYPASS_CTL1_VALID_M |
BYPASS_CTL1_OFFTRST_M;
value = (sec & BYPASS_CTL1_TIME_M) |
- BYPASS_CTL1_VALID |
+ BYPASS_CTL1_VALID |
BYPASS_CTL1_OFFTRST;
FUNC_PTR_OR_RET(adapter->bps.ops.bypass_set);
BYPASS_CTL1_OFFTRST;
FUNC_PTR_OR_RET(adapter->bps.ops.bypass_set);
@@
-275,8
+276,8
@@
s32
ixgbe_bypass_wd_timeout_store(struct rte_eth_dev *dev, u32 timeout)
{
struct ixgbe_hw *hw;
ixgbe_bypass_wd_timeout_store(struct rte_eth_dev *dev, u32 timeout)
{
struct ixgbe_hw *hw;
-
u32 status;
-
u32 mask;
+ u32 status;
+ u32 mask;
s32 ret_val;
struct ixgbe_adapter *adapter = IXGBE_DEV_TO_ADPATER(dev);
s32 ret_val;
struct ixgbe_adapter *adapter = IXGBE_DEV_TO_ADPATER(dev);
@@
-284,7
+285,7
@@
ixgbe_bypass_wd_timeout_store(struct rte_eth_dev *dev, u32 timeout)
FUNC_PTR_OR_ERR_RET(adapter->bps.ops.bypass_set, -ENOTSUP);
/* disable the timer with timeout of zero */
FUNC_PTR_OR_ERR_RET(adapter->bps.ops.bypass_set, -ENOTSUP);
/* disable the timer with timeout of zero */
- if (timeout == RTE_BYPASS_TMT_OFF) {
+ if (timeout == RTE_
PMD_IXGBE_
BYPASS_TMT_OFF) {
status = 0x0; /* WDG enable off */
mask = BYPASS_WDT_ENABLE_M;
} else {
status = 0x0; /* WDG enable off */
mask = BYPASS_WDT_ENABLE_M;
} else {
@@
-355,7
+356,7
@@
ixgbe_bypass_wd_timeout_show(struct rte_eth_dev *dev, u32 *wd_timeout)
wdg = by_ctl & BYPASS_WDT_ENABLE_M;
if (!wdg)
wdg = by_ctl & BYPASS_WDT_ENABLE_M;
if (!wdg)
- *wd_timeout = RTE_BYPASS_TMT_OFF;
+ *wd_timeout = RTE_
PMD_IXGBE_
BYPASS_TMT_OFF;
else
*wd_timeout = (by_ctl >> BYPASS_WDT_TIME_SHIFT) &
BYPASS_WDT_MASK;
else
*wd_timeout = (by_ctl >> BYPASS_WDT_TIME_SHIFT) &
BYPASS_WDT_MASK;