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net/failsafe: fix RSS hash offload reporting
[dpdk.git]
/
drivers
/
net
/
mlx5
/
mlx5.c
diff --git
a/drivers/net/mlx5/mlx5.c
b/drivers/net/mlx5/mlx5.c
index
e47ad6b
..
aae2ef9
100644
(file)
--- a/
drivers/net/mlx5/mlx5.c
+++ b/
drivers/net/mlx5/mlx5.c
@@
-11,8
+11,8
@@
#include <errno.h>
#include <rte_malloc.h>
#include <errno.h>
#include <rte_malloc.h>
-#include <
rte_
ethdev_driver.h>
-#include <
rte_
ethdev_pci.h>
+#include <ethdev_driver.h>
+#include <ethdev_pci.h>
#include <rte_pci.h>
#include <rte_bus_pci.h>
#include <rte_common.h>
#include <rte_pci.h>
#include <rte_bus_pci.h>
#include <rte_common.h>
@@
-44,9
+44,6
@@
/* Device parameter to enable RX completion queue compression. */
#define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
/* Device parameter to enable RX completion queue compression. */
#define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
-/* Device parameter to enable RX completion entry padding to 128B. */
-#define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
-
/* Device parameter to enable padding Rx packet to cacheline size. */
#define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
/* Device parameter to enable padding Rx packet to cacheline size. */
#define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
@@
-939,14
+936,6
@@
mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
goto error;
}
if (sh->devx) {
goto error;
}
if (sh->devx) {
- /* Query the EQN for this core. */
- err = mlx5_glue->devx_query_eqn(sh->ctx, 0, &sh->eqn);
- if (err) {
- rte_errno = errno;
- DRV_LOG(ERR, "Failed to query event queue number %d.",
- rte_errno);
- goto error;
- }
err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
if (err) {
DRV_LOG(ERR, "Fail to extract pdn from PD");
err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
if (err) {
DRV_LOG(ERR, "Fail to extract pdn from PD");
@@
-1019,6
+1008,7
@@
mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
/* Add context to the global device list. */
LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
/* Add context to the global device list. */
LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
+ rte_spinlock_init(&sh->geneve_tlv_opt_sl);
exit:
pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
return sh;
exit:
pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
return sh;
@@
-1117,6
+1107,7
@@
mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
mlx5_glue->devx_free_uar(sh->devx_rx_uar);
if (sh->ctx)
claim_zero(mlx5_glue->close_device(sh->ctx));
mlx5_glue->devx_free_uar(sh->devx_rx_uar);
if (sh->ctx)
claim_zero(mlx5_glue->close_device(sh->ctx));
+ MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
pthread_mutex_destroy(&sh->txpp.mutex);
mlx5_free(sh);
return;
pthread_mutex_destroy(&sh->txpp.mutex);
mlx5_free(sh);
return;
@@
-1260,13
+1251,13
@@
mlx5_proc_priv_init(struct rte_eth_dev *dev)
*/
ppriv_size =
sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
*/
ppriv_size =
sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
- ppriv = mlx5_malloc(MLX5_MEM_RTE
, ppriv_size, RTE_CACHE_LINE_SIZE
,
- dev->device->numa_node);
+ ppriv = mlx5_malloc(MLX5_MEM_RTE
| MLX5_MEM_ZERO, ppriv_size
,
+
RTE_CACHE_LINE_SIZE,
dev->device->numa_node);
if (!ppriv) {
rte_errno = ENOMEM;
return -rte_errno;
}
if (!ppriv) {
rte_errno = ENOMEM;
return -rte_errno;
}
- ppriv->uar_table_sz = p
priv_size
;
+ ppriv->uar_table_sz = p
riv->txqs_n
;
dev->process_private = ppriv;
return 0;
}
dev->process_private = ppriv;
return 0;
}
@@
-1277,7
+1268,7
@@
mlx5_proc_priv_init(struct rte_eth_dev *dev)
* @param dev
* Pointer to Ethernet device structure.
*/
* @param dev
* Pointer to Ethernet device structure.
*/
-
static
void
+void
mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
{
if (!dev->process_private)
mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
{
if (!dev->process_private)
@@
-1633,8
+1624,6
@@
mlx5_args_check(const char *key, const char *val, void *opaque)
}
config->cqe_comp = !!tmp;
config->cqe_comp_fmt = tmp;
}
config->cqe_comp = !!tmp;
config->cqe_comp_fmt = tmp;
- } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
- config->cqe_pad = !!tmp;
} else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
config->hw_padding = !!tmp;
} else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
} else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
config->hw_padding = !!tmp;
} else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
@@
-1763,7
+1752,6
@@
mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
{
const char **params = (const char *[]){
MLX5_RXQ_CQE_COMP_EN,
{
const char **params = (const char *[]){
MLX5_RXQ_CQE_COMP_EN,
- MLX5_RXQ_CQE_PAD_EN,
MLX5_RXQ_PKT_PAD_EN,
MLX5_RX_MPRQ_EN,
MLX5_RX_MPRQ_LOG_STRIDE_NUM,
MLX5_RXQ_PKT_PAD_EN,
MLX5_RX_MPRQ_EN,
MLX5_RX_MPRQ_LOG_STRIDE_NUM,