+ struct ibv_device_attr_ex device_attr; /* Device properties. */
+ struct rte_pci_device *pci_dev; /* Backend PCI device. */
+ LIST_ENTRY(mlx5_ibv_shared) mem_event_cb;
+ /**< Called by memory event callback. */
+ struct {
+ uint32_t dev_gen; /* Generation number to flush local caches. */
+ rte_rwlock_t rwlock; /* MR Lock. */
+ struct mlx5_mr_btree cache; /* Global MR cache table. */
+ struct mlx5_mr_list mr_list; /* Registered MR list. */
+ struct mlx5_mr_list mr_free_list; /* Freed MR list. */
+ } mr;
+ /* Shared DV/DR flow data section. */
+ pthread_mutex_t dv_mutex; /* DV context mutex. */
+ uint32_t dv_refcnt; /* DV/DR data reference counter. */
+ void *fdb_domain; /* FDB Direct Rules name space handle. */
+ struct mlx5_flow_tbl_resource fdb_tbl[MLX5_MAX_TABLES_FDB];
+ /* FDB Direct Rules tables. */
+ void *rx_domain; /* RX Direct Rules name space handle. */
+ struct mlx5_flow_tbl_resource rx_tbl[MLX5_MAX_TABLES];
+ /* RX Direct Rules tables. */
+ void *tx_domain; /* TX Direct Rules name space handle. */
+ struct mlx5_flow_tbl_resource tx_tbl[MLX5_MAX_TABLES];
+ void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
+ /* TX Direct Rules tables/ */
+ LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
+ LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps;
+ LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
+ LIST_HEAD(tag, mlx5_flow_dv_tag_resource) tags;
+ LIST_HEAD(jump, mlx5_flow_dv_jump_tbl_resource) jump_tbl;
+ LIST_HEAD(port_id_action_list, mlx5_flow_dv_port_id_action_resource)
+ port_id_action_list; /* List of port ID actions. */
+ /* Shared interrupt handler section. */
+ pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
+ uint32_t intr_cnt; /* Interrupt handler reference counter. */
+ struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
+ struct mlx5_ibv_shared_port port[]; /* per device port data array. */
+};
+
+/* Per-process private structure. */
+struct mlx5_proc_priv {
+ size_t uar_table_sz;
+ /* Size of UAR register table. */
+ void *uar_table[];
+ /* Table of UAR registers for each process. */
+};
+
+#define MLX5_PROC_PRIV(port_id) \
+ ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
+
+struct mlx5_priv {
+ struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
+ struct mlx5_ibv_shared *sh; /* Shared IB device context. */
+ uint32_t ibv_port; /* IB device port number. */
+ struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */