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net/octeontx2: support VLAN based RSS hash
[dpdk.git]
/
drivers
/
net
/
mlx5
/
mlx5_flow.c
diff --git
a/drivers/net/mlx5/mlx5_flow.c
b/drivers/net/mlx5/mlx5_flow.c
index
e83cf83
..
ffa7646
100644
(file)
--- a/
drivers/net/mlx5/mlx5_flow.c
+++ b/
drivers/net/mlx5/mlx5_flow.c
@@
-353,7
+353,7
@@
mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
case MLX5_METADATA_FDB:
switch (config->dv_xmeta_en) {
case MLX5_XMETA_MODE_LEGACY:
case MLX5_METADATA_FDB:
switch (config->dv_xmeta_en) {
case MLX5_XMETA_MODE_LEGACY:
- return REG_NON
E
;
+ return REG_NON;
case MLX5_XMETA_MODE_META16:
return REG_C_0;
case MLX5_XMETA_MODE_META32:
case MLX5_XMETA_MODE_META16:
return REG_C_0;
case MLX5_XMETA_MODE_META32:
@@
-363,7
+363,7
@@
mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
case MLX5_FLOW_MARK:
switch (config->dv_xmeta_en) {
case MLX5_XMETA_MODE_LEGACY:
case MLX5_FLOW_MARK:
switch (config->dv_xmeta_en) {
case MLX5_XMETA_MODE_LEGACY:
- return REG_NON
E
;
+ return REG_NON;
case MLX5_XMETA_MODE_META16:
return REG_C_1;
case MLX5_XMETA_MODE_META32:
case MLX5_XMETA_MODE_META16:
return REG_C_1;
case MLX5_XMETA_MODE_META32:
@@
-381,7
+381,7
@@
mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
return priv->mtr_color_reg != REG_C_2 ? REG_C_2 :
REG_C_3;
case MLX5_MTR_COLOR:
return priv->mtr_color_reg != REG_C_2 ? REG_C_2 :
REG_C_3;
case MLX5_MTR_COLOR:
- MLX5_ASSERT(priv->mtr_color_reg != REG_NON
E
);
+ MLX5_ASSERT(priv->mtr_color_reg != REG_NON);
return priv->mtr_color_reg;
case MLX5_COPY_MARK:
/*
return priv->mtr_color_reg;
case MLX5_COPY_MARK:
/*
@@
-404,7
+404,7
@@
mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
return rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ITEM,
NULL, "invalid tag id");
return rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ITEM,
NULL, "invalid tag id");
- if (config->flow_mreg_c[id + start_reg - REG_C_0] == REG_NON
E
)
+ if (config->flow_mreg_c[id + start_reg - REG_C_0] == REG_NON)
return rte_flow_error_set(error, ENOTSUP,
RTE_FLOW_ERROR_TYPE_ITEM,
NULL, "unsupported tag id");
return rte_flow_error_set(error, ENOTSUP,
RTE_FLOW_ERROR_TYPE_ITEM,
NULL, "unsupported tag id");
@@
-421,7
+421,7
@@
mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
RTE_FLOW_ERROR_TYPE_ITEM,
NULL, "invalid tag id");
if (config->flow_mreg_c
RTE_FLOW_ERROR_TYPE_ITEM,
NULL, "invalid tag id");
if (config->flow_mreg_c
- [id + 1 + start_reg - REG_C_0] != REG_NON
E
)
+ [id + 1 + start_reg - REG_C_0] != REG_NON)
return config->flow_mreg_c
[id + 1 + start_reg - REG_C_0];
return rte_flow_error_set(error, ENOTSUP,
return config->flow_mreg_c
[id + 1 + start_reg - REG_C_0];
return rte_flow_error_set(error, ENOTSUP,
@@
-459,7
+459,7
@@
mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev)
* - reg_c's are preserved across different domain (FDB and NIC) on
* packet loopback by flow lookup miss.
*/
* - reg_c's are preserved across different domain (FDB and NIC) on
* packet loopback by flow lookup miss.
*/
- return config->flow_mreg_c[2] != REG_NON
E
;
+ return config->flow_mreg_c[2] != REG_NON;
}
/**
}
/**
@@
-2876,10
+2876,10
@@
flow_check_meter_action(const struct rte_flow_action actions[], uint32_t *mtr)
}
/**
}
/**
- * Check if the flow should be split
ed
due to hairpin.
+ * Check if the flow should be split due to hairpin.
* The reason for the split is that in current HW we can't
* The reason for the split is that in current HW we can't
- * support encap
on Rx, so if a flow have encap we move it
- * to Tx.
+ * support encap
and push-vlan on Rx, so if a flow contains
+ * t
hese actions we move it t
o Tx.
*
* @param dev
* Pointer to Ethernet device.
*
* @param dev
* Pointer to Ethernet device.
@@
-2899,7
+2899,7
@@
flow_check_hairpin_split(struct rte_eth_dev *dev,
{
int queue_action = 0;
int action_n = 0;
{
int queue_action = 0;
int action_n = 0;
- int
encap
= 0;
+ int
split
= 0;
const struct rte_flow_action_queue *queue;
const struct rte_flow_action_rss *rss;
const struct rte_flow_action_raw_encap *raw_encap;
const struct rte_flow_action_queue *queue;
const struct rte_flow_action_rss *rss;
const struct rte_flow_action_raw_encap *raw_encap;
@@
-2930,7
+2930,10
@@
flow_check_hairpin_split(struct rte_eth_dev *dev,
break;
case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
break;
case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
- encap = 1;
+ case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
+ case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
+ case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
+ split++;
action_n++;
break;
case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
action_n++;
break;
case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
@@
-2938,7
+2941,7
@@
flow_check_hairpin_split(struct rte_eth_dev *dev,
if (raw_encap->size >
(sizeof(struct rte_flow_item_eth) +
sizeof(struct rte_flow_item_ipv4)))
if (raw_encap->size >
(sizeof(struct rte_flow_item_eth) +
sizeof(struct rte_flow_item_ipv4)))
-
encap = 1
;
+
split++
;
action_n++;
break;
default:
action_n++;
break;
default:
@@
-2946,7
+2949,7
@@
flow_check_hairpin_split(struct rte_eth_dev *dev,
break;
}
}
break;
}
}
- if (
encap == 1
&& queue_action)
+ if (
split
&& queue_action)
return action_n;
return 0;
}
return action_n;
return 0;
}
@@
-3008,7
+3011,7
@@
flow_mreg_add_copy_action(struct rte_eth_dev *dev, uint32_t mark_id,
};
struct mlx5_flow_action_copy_mreg cp_mreg = {
.dst = REG_B,
};
struct mlx5_flow_action_copy_mreg cp_mreg = {
.dst = REG_B,
- .src =
0
,
+ .src =
REG_NON
,
};
struct rte_flow_action_jump jump = {
.group = MLX5_FLOW_MREG_ACT_TABLE_GROUP,
};
struct rte_flow_action_jump jump = {
.group = MLX5_FLOW_MREG_ACT_TABLE_GROUP,
@@
-3388,7
+3391,8
@@
flow_mreg_update_copy_table(struct rte_eth_dev *dev,
/**
* Split the hairpin flow.
/**
* Split the hairpin flow.
- * Since HW can't support encap on Rx we move the encap to Tx.
+ * Since HW can't support encap and push-vlan on Rx, we move these
+ * actions to Tx.
* If the count action is after the encap then we also
* move the count action. in this case the count will also measure
* the outer bytes.
* If the count action is after the encap then we also
* move the count action. in this case the count will also measure
* the outer bytes.
@@
-3432,6
+3436,9
@@
flow_hairpin_split(struct rte_eth_dev *dev,
switch (actions->type) {
case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
switch (actions->type) {
case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
+ case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
+ case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
+ case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
rte_memcpy(actions_tx, actions,
sizeof(struct rte_flow_action));
actions_tx++;
rte_memcpy(actions_tx, actions,
sizeof(struct rte_flow_action));
actions_tx++;
@@
-3492,7
+3499,7
@@
flow_hairpin_split(struct rte_eth_dev *dev,
actions_rx++;
set_tag = (void *)actions_rx;
set_tag->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_RX, 0, NULL);
actions_rx++;
set_tag = (void *)actions_rx;
set_tag->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_RX, 0, NULL);
- MLX5_ASSERT(set_tag->id > REG_NON
E
);
+ MLX5_ASSERT(set_tag->id > REG_NON);
set_tag->data = *flow_id;
tag_action->conf = set_tag;
/* Create Tx item list. */
set_tag->data = *flow_id;
tag_action->conf = set_tag;
/* Create Tx item list. */
@@
-3504,14
+3511,13
@@
flow_hairpin_split(struct rte_eth_dev *dev,
tag_item = (void *)addr;
tag_item->data = *flow_id;
tag_item->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_TX, 0, NULL);
tag_item = (void *)addr;
tag_item->data = *flow_id;
tag_item->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_TX, 0, NULL);
- MLX5_ASSERT(set_tag->id > REG_NON
E
);
+ MLX5_ASSERT(set_tag->id > REG_NON);
item->spec = tag_item;
addr += sizeof(struct mlx5_rte_flow_item_tag);
tag_item = (void *)addr;
tag_item->data = UINT32_MAX;
tag_item->id = UINT16_MAX;
item->mask = tag_item;
item->spec = tag_item;
addr += sizeof(struct mlx5_rte_flow_item_tag);
tag_item = (void *)addr;
tag_item->data = UINT32_MAX;
tag_item->id = UINT16_MAX;
item->mask = tag_item;
- addr += sizeof(struct mlx5_rte_flow_item_tag);
item->last = NULL;
item++;
item->type = RTE_FLOW_ITEM_TYPE_END;
item->last = NULL;
item++;
item->type = RTE_FLOW_ITEM_TYPE_END;
@@
-4060,7
+4066,7
@@
flow_create_split_metadata(struct rte_eth_dev *dev,
/* Internal PMD action to set register. */
struct mlx5_rte_flow_item_tag q_tag_spec = {
.data = qrss_id,
/* Internal PMD action to set register. */
struct mlx5_rte_flow_item_tag q_tag_spec = {
.data = qrss_id,
- .id =
0
,
+ .id =
REG_NON
,
};
struct rte_flow_item q_items[] = {
{
};
struct rte_flow_item q_items[] = {
{
@@
-5125,6
+5131,10
@@
mlx5_flow_isolate(struct rte_eth_dev *dev,
dev->dev_ops = &mlx5_os_dev_ops_isolate;
else
dev->dev_ops = &mlx5_os_dev_ops;
dev->dev_ops = &mlx5_os_dev_ops_isolate;
else
dev->dev_ops = &mlx5_os_dev_ops;
+
+ dev->rx_descriptor_status = mlx5_rx_descriptor_status;
+ dev->tx_descriptor_status = mlx5_tx_descriptor_status;
+
return 0;
}
return 0;
}
@@
-5967,6
+5977,11
@@
next_container:
goto set_alarm;
dcs = (struct mlx5_devx_obj *)(uintptr_t)rte_atomic64_read
(&pool->a64_dcs);
goto set_alarm;
dcs = (struct mlx5_devx_obj *)(uintptr_t)rte_atomic64_read
(&pool->a64_dcs);
+ if (dcs->id & (MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT - 1)) {
+ /* Pool without valid counter. */
+ pool->raw_hw = NULL;
+ goto next_pool;
+ }
offset = batch ? 0 : dcs->id % MLX5_COUNTERS_PER_POOL;
/*
* Identify the counters released between query trigger and query
offset = batch ? 0 : dcs->id % MLX5_COUNTERS_PER_POOL;
/*
* Identify the counters released between query trigger and query
@@
-5991,6
+6006,7
@@
next_container:
pool->raw_hw->min_dcs_id = dcs->id;
LIST_REMOVE(pool->raw_hw, next);
sh->cmng.pending_queries++;
pool->raw_hw->min_dcs_id = dcs->id;
LIST_REMOVE(pool->raw_hw, next);
sh->cmng.pending_queries++;
+next_pool:
pool_index++;
if (pool_index >= rte_atomic16_read(&cont->n_valid)) {
batch ^= 0x1;
pool_index++;
if (pool_index >= rte_atomic16_read(&cont->n_valid)) {
batch ^= 0x1;
@@
-6062,7
+6078,7
@@
mlx5_flow_aging_check(struct mlx5_dev_ctx_shared *sh,
if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
continue;
if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER))
if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
continue;
if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER))
-
_
rte_eth_dev_callback_process
+ rte_eth_dev_callback_process
(&rte_eth_devices[sh->port[i].devx_ih_port_id],
RTE_ETH_EVENT_FLOW_AGED, NULL);
age_info->flags = 0;
(&rte_eth_devices[sh->port[i].devx_ih_port_id],
RTE_ETH_EVENT_FLOW_AGED, NULL);
age_info->flags = 0;
@@
-6102,7
+6118,7
@@
mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh,
pool->raw = pool->raw_hw;
rte_spinlock_unlock(&pool->sl);
/* Be sure the new raw counters data is updated in memory. */
pool->raw = pool->raw_hw;
rte_spinlock_unlock(&pool->sl);
/* Be sure the new raw counters data is updated in memory. */
- rte_
c
io_wmb();
+ rte_io_wmb();
if (!TAILQ_EMPTY(&pool->counters[query_gen])) {
rte_spinlock_lock(&cont->csl);
TAILQ_CONCAT(&cont->counters,
if (!TAILQ_EMPTY(&pool->counters[query_gen])) {
rte_spinlock_lock(&cont->csl);
TAILQ_CONCAT(&cont->counters,
@@
-6224,7
+6240,7
@@
mlx5_flow_discover_mreg_c(struct rte_eth_dev *dev)
flow_list_destroy(dev, NULL, flow_idx);
}
for (; n < MLX5_MREG_C_NUM; ++n)
flow_list_destroy(dev, NULL, flow_idx);
}
for (; n < MLX5_MREG_C_NUM; ++n)
- config->flow_mreg_c[n] = REG_NON
E
;
+ config->flow_mreg_c[n] = REG_NON;
return 0;
}
return 0;
}