+/* Sample action resource structure. */
+struct mlx5_flow_dv_sample_resource {
+ ILIST_ENTRY(uint32_t)next; /**< Pointer to next element. */
+ uint32_t refcnt; /**< Reference counter. */
+ void *verbs_action; /**< Verbs sample action object. */
+ uint8_t ft_type; /** Flow Table Type */
+ uint32_t ft_id; /** Flow Table Level */
+ uint32_t ratio; /** Sample Ratio */
+ uint64_t set_action; /** Restore reg_c0 value */
+ void *normal_path_tbl; /** Flow Table pointer */
+ void *default_miss; /** default_miss dr_action. */
+ struct mlx5_flow_sub_actions_idx sample_idx;
+ /**< Action index resources. */
+ struct mlx5_flow_sub_actions_list sample_act;
+ /**< Action resources. */
+};
+
+#define MLX5_MAX_DEST_NUM 2
+
+/* Destination array action resource structure. */
+struct mlx5_flow_dv_dest_array_resource {
+ ILIST_ENTRY(uint32_t)next; /**< Pointer to next element. */
+ uint32_t refcnt; /**< Reference counter. */
+ uint8_t ft_type; /** Flow Table Type */
+ uint8_t num_of_dest; /**< Number of destination actions. */
+ void *action; /**< Pointer to the rdma core action. */
+ struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
+ /**< Action index resources. */
+ struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
+ /**< Action resources. */
+};
+
+/* Verbs specification header. */
+struct ibv_spec_header {
+ enum ibv_flow_spec_type type;
+ uint16_t size;
+};
+
+/* RSS description. */
+struct mlx5_flow_rss_desc {
+ uint32_t level;
+ uint32_t queue_num; /**< Number of entries in @p queue. */
+ uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
+ uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
+ uint16_t queue[]; /**< Destination queues to redirect traffic to. */
+};
+
+/* PMD flow priority for tunnel */
+#define MLX5_TUNNEL_PRIO_GET(rss_desc) \
+ ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
+
+
+/** Device flow handle structure for DV mode only. */
+struct mlx5_flow_handle_dv {
+ /* Flow DV api: */
+ struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
+ struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
+ /**< Pointer to modify header resource in cache. */
+ uint32_t rix_encap_decap;
+ /**< Index to encap/decap resource in cache. */
+ uint32_t rix_push_vlan;
+ /**< Index to push VLAN action resource in cache. */
+ uint32_t rix_tag;
+ /**< Index to the tag action. */
+ uint32_t rix_sample;
+ /**< Index to sample action resource in cache. */
+ uint32_t rix_dest_array;
+ /**< Index to destination array resource in cache. */
+} __rte_packed;
+
+/** Device flow handle structure: used both for creating & destroying. */
+struct mlx5_flow_handle {
+ SILIST_ENTRY(uint32_t)next;
+ struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
+ /**< Index to next device flow handle. */
+ uint64_t layers;
+ /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
+ void *drv_flow; /**< pointer to driver flow object. */
+ uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */
+ uint32_t mark:1; /**< Metadate rxq mark flag. */
+ uint32_t fate_action:3; /**< Fate action type. */
+ union {
+ uint32_t rix_hrxq; /**< Hash Rx queue object index. */
+ uint32_t rix_jump; /**< Index to the jump action resource. */
+ uint32_t rix_port_id_action;
+ /**< Index to port ID action resource. */
+ uint32_t rix_fate;
+ /**< Generic value indicates the fate action. */
+ uint32_t rix_default_fate;
+ /**< Indicates default miss fate action. */
+ };
+#ifdef HAVE_IBV_FLOW_DV_SUPPORT
+ struct mlx5_flow_handle_dv dvh;
+#endif
+} __rte_packed;
+
+/*
+ * Size for Verbs device flow handle structure only. Do not use the DV only
+ * structure in Verbs. No DV flows attributes will be accessed.
+ * Macro offsetof() could also be used here.
+ */
+#ifdef HAVE_IBV_FLOW_DV_SUPPORT
+#define MLX5_FLOW_HANDLE_VERBS_SIZE \
+ (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
+#else
+#define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
+#endif
+