+
+/** Device flow handle structure for DV mode only. */
+struct mlx5_flow_handle_dv {
+ /* Flow DV api: */
+ struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
+ struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
+ /**< Pointer to modify header resource in cache. */
+ uint32_t rix_encap_decap;
+ /**< Index to encap/decap resource in cache. */
+ uint32_t rix_push_vlan;
+ /**< Index to push VLAN action resource in cache. */
+ uint32_t rix_tag;
+ /**< Index to the tag action. */
+} __rte_packed;
+
+/** Device flow handle structure: used both for creating & destroying. */
+struct mlx5_flow_handle {
+ SILIST_ENTRY(uint32_t)next;
+ struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
+ /**< Index to next device flow handle. */
+ uint64_t layers;
+ /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
+ void *ib_flow; /**< Verbs flow pointer. */
+ uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */
+ uint32_t mark:1; /**< Metadate rxq mark flag. */
+ uint32_t fate_action:3; /**< Fate action type. */
+ union {
+ uint32_t rix_hrxq; /**< Hash Rx queue object index. */
+ uint32_t rix_jump; /**< Index to the jump action resource. */
+ uint32_t rix_port_id_action;
+ /**< Index to port ID action resource. */
+ uint32_t rix_fate;
+ /**< Generic value indicates the fate action. */
+ };
+#ifdef HAVE_IBV_FLOW_DV_SUPPORT
+ struct mlx5_flow_handle_dv dvh;
+#endif
+} __rte_packed;
+
+/*
+ * Size for Verbs device flow handle structure only. Do not use the DV only
+ * structure in Verbs. No DV flows attributes will be accessed.
+ * Macro offsetof() could also be used here.
+ */
+#ifdef HAVE_IBV_FLOW_DV_SUPPORT
+#define MLX5_FLOW_HANDLE_VERBS_SIZE \
+ (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
+#else
+#define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
+#endif
+