- switch (reg) {
- case REG_A:
- MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a,
- rte_be_to_cpu_32(mask));
- MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a,
- rte_be_to_cpu_32(value));
- break;
- case REG_B:
- MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b,
- rte_be_to_cpu_32(mask));
- MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b,
- rte_be_to_cpu_32(value));
- break;
- case REG_C_0:
- MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0,
- rte_be_to_cpu_32(mask));
- MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0,
- rte_be_to_cpu_32(value));
- break;
- case REG_C_1:
- MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1,
- rte_be_to_cpu_32(mask));
- MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1,
- rte_be_to_cpu_32(value));
- break;
- case REG_C_2:
- MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2,
- rte_be_to_cpu_32(mask));
- MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2,
- rte_be_to_cpu_32(value));
- break;
- case REG_C_3:
- MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3,
- rte_be_to_cpu_32(mask));
- MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3,
- rte_be_to_cpu_32(value));
- break;
- case REG_C_4:
- MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4,
- rte_be_to_cpu_32(mask));
- MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4,
- rte_be_to_cpu_32(value));
- break;
- case REG_C_5:
- MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5,
- rte_be_to_cpu_32(mask));
- MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5,
- rte_be_to_cpu_32(value));
- break;
- case REG_C_6:
- MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6,
- rte_be_to_cpu_32(mask));
- MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6,
- rte_be_to_cpu_32(value));
- break;
- case REG_C_7:
- MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7,
- rte_be_to_cpu_32(mask));
- MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7,
- rte_be_to_cpu_32(value));
- break;
- }