+
+ return rx_queue_count(rxq);
+}
+
+#define CLB_VAL_IDX 0
+#define CLB_MSK_IDX 1
+static int
+mlx5_monitor_callback(const uint64_t value,
+ const uint64_t opaque[RTE_POWER_MONITOR_OPAQUE_SZ])
+{
+ const uint64_t m = opaque[CLB_MSK_IDX];
+ const uint64_t v = opaque[CLB_VAL_IDX];
+
+ return (value & m) == v ? -1 : 0;
+}
+
+int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
+{
+ struct mlx5_rxq_data *rxq = rx_queue;
+ const unsigned int cqe_num = 1 << rxq->cqe_n;
+ const unsigned int cqe_mask = cqe_num - 1;
+ const uint16_t idx = rxq->cq_ci & cqe_num;
+ volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask];
+
+ if (unlikely(rxq->cqes == NULL)) {