-/* Compressed CQE context. */
-struct rxq_zip {
- uint16_t ai; /* Array index. */
- uint16_t ca; /* Current array index. */
- uint16_t na; /* Next array index. */
- uint16_t cq_ci; /* The next CQE. */
- uint32_t cqe_cnt; /* Number of CQEs. */
-};
-
-/* Multi-Packet RQ buffer header. */
-struct mlx5_mprq_buf {
- struct rte_mempool *mp;
- rte_atomic16_t refcnt; /* Atomically accessed refcnt. */
- uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
-} __rte_cache_aligned;
-
-/* Get pointer to the first stride. */
-#define mlx5_mprq_buf_addr(ptr) ((ptr) + 1)
-
-#define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
-#define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
-
-enum mlx5_rxq_err_state {
- MLX5_RXQ_ERR_STATE_NO_ERROR = 0,
- MLX5_RXQ_ERR_STATE_NEED_RESET,
- MLX5_RXQ_ERR_STATE_NEED_READY,
-};
-
-/* RX queue descriptor. */
-struct mlx5_rxq_data {
- unsigned int csum:1; /* Enable checksum offloading. */
- unsigned int hw_timestamp:1; /* Enable HW timestamp. */
- unsigned int vlan_strip:1; /* Enable VLAN stripping. */
- unsigned int crc_present:1; /* CRC must be subtracted. */
- unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
- unsigned int cqe_n:4; /* Log 2 of CQ elements. */
- unsigned int elts_n:4; /* Log 2 of Mbufs. */
- unsigned int rss_hash:1; /* RSS hash result is enabled. */
- unsigned int mark:1; /* Marked flow available on the queue. */
- unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
- unsigned int strd_sz_n:4; /* Log 2 of stride size. */
- unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
- unsigned int err_state:2; /* enum mlx5_rxq_err_state. */
- unsigned int :4; /* Remaining bits. */
- volatile uint32_t *rq_db;
- volatile uint32_t *cq_db;
- uint16_t port_id;
- uint32_t rq_ci;
- uint16_t consumed_strd; /* Number of consumed strides in WQE. */
- uint32_t rq_pi;
- uint32_t cq_ci;
- uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */
- union {
- struct rxq_zip zip; /* Compressed context. */
- uint16_t decompressed;
- /* Number of ready mbufs decompressed from the CQ. */
- };
- struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
- uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
- volatile void *wqes;
- volatile struct mlx5_cqe(*cqes)[];
- RTE_STD_C11
- union {
- struct rte_mbuf *(*elts)[];
- struct mlx5_mprq_buf *(*mprq_bufs)[];
- };
- struct rte_mempool *mp;
- struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
- struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
- uint16_t idx; /* Queue index. */
- struct mlx5_rxq_stats stats;
- uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */
- struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
- void *cq_uar; /* CQ user access region. */
- uint32_t cqn; /* CQ number. */
- uint8_t cq_arm_sn; /* CQ arm seq number. */
-#ifndef RTE_ARCH_64
- rte_spinlock_t *uar_lock_cq;
- /* CQ (UAR) access lock required for 32bit implementations */
-#endif
- uint32_t tunnel; /* Tunnel information. */
-} __rte_cache_aligned;
-
-enum mlx5_rxq_obj_type {
- MLX5_RXQ_OBJ_TYPE_IBV, /* mlx5_rxq_obj with ibv_wq. */
- MLX5_RXQ_OBJ_TYPE_DEVX_RQ, /* mlx5_rxq_obj with mlx5_devx_rq. */
-};
-
-/* Verbs/DevX Rx queue elements. */
-struct mlx5_rxq_obj {
- LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */
- rte_atomic32_t refcnt; /* Reference counter. */
- struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
- struct ibv_cq *cq; /* Completion Queue. */
- enum mlx5_rxq_obj_type type;
- RTE_STD_C11
- union {
- struct ibv_wq *wq; /* Work Queue. */
- struct mlx5_devx_obj *rq; /* DevX object for Rx Queue. */
- };
- struct ibv_comp_channel *channel;
-};
-
-/* RX queue control descriptor. */
-struct mlx5_rxq_ctrl {
- struct mlx5_rxq_data rxq; /* Data path structure. */
- LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
- rte_atomic32_t refcnt; /* Reference counter. */
- struct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */
- struct mlx5_priv *priv; /* Back pointer to private data. */
- unsigned int socket; /* CPU socket ID for allocations. */
- unsigned int irq:1; /* Whether IRQ is enabled. */
- uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
- uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */
- uint32_t wqn; /* WQ number. */
- uint16_t dump_file_n; /* Number of dump files. */
- uint32_t dbr_umem_id; /* Storing door-bell information, */
- uint64_t dbr_offset; /* needed when freeing door-bell. */
- struct mlx5dv_devx_umem *wq_umem; /* WQ buffer registration info. */
-};
-
-enum mlx5_ind_tbl_type {
- MLX5_IND_TBL_TYPE_IBV,
- MLX5_IND_TBL_TYPE_DEVX,
-};
-
-/* Indirection table. */
-struct mlx5_ind_table_obj {
- LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */
- rte_atomic32_t refcnt; /* Reference counter. */
- enum mlx5_ind_tbl_type type;
- RTE_STD_C11
- union {
- struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
- struct mlx5_devx_obj *rqt; /* DevX RQT object. */
- };
- uint32_t queues_n; /**< Number of queues in the list. */
- uint16_t queues[]; /**< Queue list. */
-};
-
-/* Hash Rx queue. */
-struct mlx5_hrxq {
- LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */
- rte_atomic32_t refcnt; /* Reference counter. */
- struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
- RTE_STD_C11
- union {
- struct ibv_qp *qp; /* Verbs queue pair. */
- struct mlx5_devx_obj *tir; /* DevX TIR object. */
- };
-#ifdef HAVE_IBV_FLOW_DV_SUPPORT
- void *action; /* DV QP action pointer. */
-#endif
- uint64_t hash_fields; /* Verbs Hash fields. */
- uint32_t rss_key_len; /* Hash key length in bytes. */
- uint8_t rss_key[]; /* Hash key. */
-};
-
-/* TX queue send local data. */
-__extension__
-struct mlx5_txq_local {
- struct mlx5_wqe *wqe_last; /* last sent WQE pointer. */
- struct rte_mbuf *mbuf; /* first mbuf to process. */
- uint16_t pkts_copy; /* packets copied to elts. */
- uint16_t pkts_sent; /* packets sent. */
- uint16_t elts_free; /* available elts remain. */
- uint16_t wqe_free; /* available wqe remain. */
- uint16_t mbuf_off; /* data offset in current mbuf. */
- uint16_t mbuf_nseg; /* number of remaining mbuf. */
-};
-
-/* TX queue descriptor. */
-__extension__
-struct mlx5_txq_data {
- uint16_t elts_head; /* Current counter in (*elts)[]. */
- uint16_t elts_tail; /* Counter of first element awaiting completion. */
- uint16_t elts_comp; /* elts index since last completion request. */
- uint16_t elts_s; /* Number of mbuf elements. */
- uint16_t elts_m; /* Mask for mbuf elements indices. */
- /* Fields related to elts mbuf storage. */
- uint16_t wqe_ci; /* Consumer index for work queue. */
- uint16_t wqe_pi; /* Producer index for work queue. */
- uint16_t wqe_s; /* Number of WQ elements. */
- uint16_t wqe_m; /* Mask Number for WQ elements. */
- uint16_t wqe_comp; /* WQE index since last completion request. */
- uint16_t wqe_thres; /* WQE threshold to request completion in CQ. */
- /* WQ related fields. */
- uint16_t cq_ci; /* Consumer index for completion queue. */
-#ifndef NDEBUG
- uint16_t cq_pi; /* Counter of issued CQE "always" requests. */
-#endif
- uint16_t cqe_s; /* Number of CQ elements. */
- uint16_t cqe_m; /* Mask for CQ indices. */
- /* CQ related fields. */
- uint16_t elts_n:4; /* elts[] length (in log2). */
- uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
- uint16_t wqe_n:4; /* Number of WQ elements (in log2). */
- uint16_t tso_en:1; /* When set hardware TSO is enabled. */
- uint16_t tunnel_en:1;
- /* When set TX offload for tunneled packets are supported. */
- uint16_t swp_en:1; /* Whether SW parser is enabled. */
- uint16_t vlan_en:1; /* VLAN insertion in WQE is supported. */
- uint16_t inlen_send; /* Ordinary send data inline size. */
- uint16_t inlen_empw; /* eMPW max packet size to inline. */
- uint16_t inlen_mode; /* Minimal data length to inline. */
- uint32_t qp_num_8s; /* QP number shifted by 8. */
- uint64_t offloads; /* Offloads for Tx Queue. */
- struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
- struct mlx5_wqe *wqes; /* Work queue. */
- struct mlx5_wqe *wqes_end; /* Work queue array limit. */
- volatile struct mlx5_cqe *cqes; /* Completion queue. */
- volatile uint32_t *qp_db; /* Work queue doorbell. */
- volatile uint32_t *cq_db; /* Completion queue doorbell. */
- uint16_t port_id; /* Port ID of device. */
- uint16_t idx; /* Queue index. */
- struct mlx5_txq_stats stats; /* TX queue counters. */
-#ifndef RTE_ARCH_64
- rte_spinlock_t *uar_lock;
- /* UAR access lock required for 32bit implementations */
-#endif
- struct rte_mbuf *elts[0];
- /* Storage for queued packets, must be the last field. */
-} __rte_cache_aligned;
-
-/* Verbs Rx queue elements. */
-struct mlx5_txq_ibv {
- LIST_ENTRY(mlx5_txq_ibv) next; /* Pointer to the next element. */
- rte_atomic32_t refcnt; /* Reference counter. */
- struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
- struct ibv_cq *cq; /* Completion Queue. */
- struct ibv_qp *qp; /* Queue Pair. */
-};
-
-/* TX queue control descriptor. */
-struct mlx5_txq_ctrl {
- LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
- rte_atomic32_t refcnt; /* Reference counter. */
- unsigned int socket; /* CPU socket ID for allocations. */
- unsigned int max_inline_data; /* Max inline data. */
- unsigned int max_tso_header; /* Max TSO header size. */
- struct mlx5_txq_ibv *ibv; /* Verbs queue object. */
- struct mlx5_priv *priv; /* Back pointer to private data. */
- off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
- void *bf_reg; /* BlueFlame register from Verbs. */
- uint16_t dump_file_n; /* Number of dump files. */
- struct mlx5_txq_data txq; /* Data path structure. */
- /* Must be the last field in the structure, contains elts[]. */
-};
-
-#define MLX5_TX_BFREG(txq) \
- (MLX5_PROC_PRIV((txq)->port_id)->uar_table[(txq)->idx])
-
-/* mlx5_rxq.c */
-
-extern uint8_t rss_hash_default_key[];
-
-int mlx5_check_mprq_support(struct rte_eth_dev *dev);
-int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq);
-int mlx5_mprq_enabled(struct rte_eth_dev *dev);
-int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
-int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
-int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
- unsigned int socket, const struct rte_eth_rxconf *conf,
- struct rte_mempool *mp);
-void mlx5_rx_queue_release(void *dpdk_rxq);
-int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
-void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
-int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
-int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
-struct mlx5_rxq_obj *mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
- enum mlx5_rxq_obj_type type);
-int mlx5_rxq_obj_verify(struct rte_eth_dev *dev);
-struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
- uint16_t desc, unsigned int socket,
- const struct rte_eth_rxconf *conf,
- struct rte_mempool *mp);
-struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
-int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
-int mlx5_rxq_verify(struct rte_eth_dev *dev);
-int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
-int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev);
-struct mlx5_hrxq *mlx5_hrxq_new(struct rte_eth_dev *dev,
- const uint8_t *rss_key, uint32_t rss_key_len,
- uint64_t hash_fields,
- const uint16_t *queues, uint32_t queues_n,
- int tunnel __rte_unused, int lro);
-struct mlx5_hrxq *mlx5_hrxq_get(struct rte_eth_dev *dev,
- const uint8_t *rss_key, uint32_t rss_key_len,
- uint64_t hash_fields,
- const uint16_t *queues, uint32_t queues_n);
-int mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hxrq);
-int mlx5_hrxq_verify(struct rte_eth_dev *dev);
-struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev);
-void mlx5_hrxq_drop_release(struct rte_eth_dev *dev);
-uint64_t mlx5_get_rx_port_offloads(struct rte_eth_dev *dev);
-uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
-int mlx5_lro_on(struct rte_eth_dev *dev);
-
-/* mlx5_txq.c */
-
-int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
- unsigned int socket, const struct rte_eth_txconf *conf);
-void mlx5_tx_queue_release(void *dpdk_txq);
-int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd);
-struct mlx5_txq_ibv *mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
-struct mlx5_txq_ibv *mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx);
-int mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv);
-int mlx5_txq_ibv_verify(struct rte_eth_dev *dev);
-struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
- uint16_t desc, unsigned int socket,
- const struct rte_eth_txconf *conf);
-struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
-int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
-int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
-int mlx5_txq_verify(struct rte_eth_dev *dev);
-void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
-uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
-