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net/ice/base: add more macros for FDID priority
[dpdk.git]
/
drivers
/
net
/
mlx5
/
mlx5_rxtx_vec.c
diff --git
a/drivers/net/mlx5/mlx5_rxtx_vec.c
b/drivers/net/mlx5/mlx5_rxtx_vec.c
index
3815ff6
..
1518bdd
100644
(file)
--- a/
drivers/net/mlx5/mlx5_rxtx_vec.c
+++ b/
drivers/net/mlx5/mlx5_rxtx_vec.c
@@
-3,7
+3,6
@@
* Copyright 2017 Mellanox Technologies, Ltd
*/
* Copyright 2017 Mellanox Technologies, Ltd
*/
-#include <assert.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
@@
-23,18
+22,21
@@
#include <rte_mempool.h>
#include <rte_prefetch.h>
#include <rte_mempool.h>
#include <rte_prefetch.h>
+#include <mlx5_prm.h>
+
+#include "mlx5_defs.h"
#include "mlx5.h"
#include "mlx5_utils.h"
#include "mlx5_rxtx.h"
#include "mlx5_rxtx_vec.h"
#include "mlx5_autoconf.h"
#include "mlx5.h"
#include "mlx5_utils.h"
#include "mlx5_rxtx.h"
#include "mlx5_rxtx_vec.h"
#include "mlx5_autoconf.h"
-#include "mlx5_defs.h"
-#include "mlx5_prm.h"
#if defined RTE_ARCH_X86_64
#include "mlx5_rxtx_vec_sse.h"
#elif defined RTE_ARCH_ARM64
#include "mlx5_rxtx_vec_neon.h"
#if defined RTE_ARCH_X86_64
#include "mlx5_rxtx_vec_sse.h"
#elif defined RTE_ARCH_ARM64
#include "mlx5_rxtx_vec_neon.h"
+#elif defined RTE_ARCH_PPC_64
+#include "mlx5_rxtx_vec_altivec.h"
#else
#error "This should not be compiled if SIMD instructions are not supported."
#endif
#else
#error "This should not be compiled if SIMD instructions are not supported."
#endif
@@
-119,7
+121,7
@@
mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
* @return
* 1 if supported, negative errno value if not.
*/
* @return
* 1 if supported, negative errno value if not.
*/
-int __
attribute__((cold))
+int __
rte_cold
mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq)
{
struct mlx5_rxq_ctrl *ctrl =
mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq)
{
struct mlx5_rxq_ctrl *ctrl =
@@
-129,6
+131,8
@@
mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq)
return -ENOTSUP;
if (!ctrl->priv->config.rx_vec_en || rxq->sges_n != 0)
return -ENOTSUP;
return -ENOTSUP;
if (!ctrl->priv->config.rx_vec_en || rxq->sges_n != 0)
return -ENOTSUP;
+ if (rxq->lro)
+ return -ENOTSUP;
return 1;
}
return 1;
}
@@
-141,7
+145,7
@@
mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq)
* @return
* 1 if supported, negative errno value if not.
*/
* @return
* 1 if supported, negative errno value if not.
*/
-int __
attribute__((cold))
+int __
rte_cold
mlx5_check_vec_rx_support(struct rte_eth_dev *dev)
{
struct mlx5_priv *priv = dev->data->dev_private;
mlx5_check_vec_rx_support(struct rte_eth_dev *dev)
{
struct mlx5_priv *priv = dev->data->dev_private;
@@
-151,8
+155,6
@@
mlx5_check_vec_rx_support(struct rte_eth_dev *dev)
return -ENOTSUP;
if (mlx5_mprq_enabled(dev))
return -ENOTSUP;
return -ENOTSUP;
if (mlx5_mprq_enabled(dev))
return -ENOTSUP;
- if (mlx5_lro_on(dev))
- return -ENOTSUP;
/* All the configured queues should support. */
for (i = 0; i < priv->rxqs_n; ++i) {
struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
/* All the configured queues should support. */
for (i = 0; i < priv->rxqs_n; ++i) {
struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];