+} __rte_aligned(64);
+
+struct nfp_pf_dev {
+ /* Backpointer to associated pci device */
+ struct rte_pci_device *pci_dev;
+
+ /* First physical port's eth device */
+ struct rte_eth_dev *eth_dev;
+
+ /* Array of physical ports belonging to this PF */
+ struct nfp_net_hw *ports[NFP_MAX_PHYPORTS];
+
+ /* Current values for control */
+ uint32_t ctrl;
+
+ uint8_t *ctrl_bar;
+ uint8_t *tx_bar;
+ uint8_t *rx_bar;
+
+ uint8_t *qcp_cfg;
+ rte_spinlock_t reconfig_lock;
+
+ uint16_t flbufsz;
+ uint16_t device_id;
+ uint16_t vendor_id;
+ uint16_t subsystem_device_id;
+ uint16_t subsystem_vendor_id;
+#if defined(DSTQ_SELECTION)
+#if DSTQ_SELECTION
+ uint16_t device_function;
+#endif
+#endif
+
+ struct nfp_cpp *cpp;
+ struct nfp_cpp_area *ctrl_area;
+ struct nfp_cpp_area *hwqueues_area;
+ struct nfp_cpp_area *msix_area;
+
+ uint8_t *hw_queues;
+ uint8_t total_phyports;
+ bool multiport;
+
+ union eth_table_entry *eth_table;
+
+ struct nfp_hwinfo *hwinfo;
+ struct nfp_rtsym_table *sym_tbl;
+ uint32_t nfp_cpp_service_id;
+};