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net/mlx5: support connection tracking between two ports
[dpdk.git]
/
drivers
/
net
/
octeontx2
/
otx2_ethdev.h
diff --git
a/drivers/net/octeontx2/otx2_ethdev.h
b/drivers/net/octeontx2/otx2_ethdev.h
index
eb16263
..
ac50da7
100644
(file)
--- a/
drivers/net/octeontx2/otx2_ethdev.h
+++ b/
drivers/net/octeontx2/otx2_ethdev.h
@@
-13,6
+13,7
@@
#include <rte_kvargs.h>
#include <rte_mbuf.h>
#include <rte_mempool.h>
#include <rte_kvargs.h>
#include <rte_mbuf.h>
#include <rte_mempool.h>
+#include <rte_security_driver.h>
#include <rte_string_fns.h>
#include <rte_time.h>
#include <rte_string_fns.h>
#include <rte_time.h>
@@
-50,6
+51,8
@@
/* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
#define NIX_L2_OVERHEAD \
(RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
/* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
#define NIX_L2_OVERHEAD \
(RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
+#define NIX_L2_MAX_LEN \
+ (RTE_ETHER_MTU + NIX_L2_OVERHEAD)
/* HW config of frame size doesn't include FCS */
#define NIX_MAX_HW_FRS 9212
/* HW config of frame size doesn't include FCS */
#define NIX_MAX_HW_FRS 9212
@@
-79,7
+82,7
@@
#define NIX_RX_NB_SEG_MAX 6
#define NIX_CQ_ENTRY_SZ 128
#define NIX_CQ_ALIGN 512
#define NIX_RX_NB_SEG_MAX 6
#define NIX_CQ_ENTRY_SZ 128
#define NIX_CQ_ALIGN 512
-#define NIX_SQB_LOWER_THRESH
9
0
+#define NIX_SQB_LOWER_THRESH
7
0
#define LMT_SLOT_MASK 0x7f
#define NIX_RX_DEFAULT_RING_SZ 4096
#define LMT_SLOT_MASK 0x7f
#define NIX_RX_DEFAULT_RING_SZ 4096
@@
-113,9
+116,14
@@
#define CQ_TIMER_THRESH_DEFAULT 0xAULL /* ~1usec i.e (0xA * 100nsec) */
#define CQ_TIMER_THRESH_MAX 255
#define CQ_TIMER_THRESH_DEFAULT 0xAULL /* ~1usec i.e (0xA * 100nsec) */
#define CQ_TIMER_THRESH_MAX 255
+#define NIX_RSS_L3_L4_SRC_DST (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY \
+ | ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY)
+
#define NIX_RSS_OFFLOAD (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP |\
ETH_RSS_TCP | ETH_RSS_SCTP | \
#define NIX_RSS_OFFLOAD (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP |\
ETH_RSS_TCP | ETH_RSS_SCTP | \
- ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD)
+ ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD | \
+ NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | \
+ ETH_RSS_C_VLAN)
#define NIX_TX_OFFLOAD_CAPA ( \
DEV_TX_OFFLOAD_MBUF_FAST_FREE | \
#define NIX_TX_OFFLOAD_CAPA ( \
DEV_TX_OFFLOAD_MBUF_FAST_FREE | \
@@
-156,6
+164,11
@@
/* Additional timesync values. */
#define OTX2_CYCLECOUNTER_MASK 0xffffffffffffffffULL
/* Additional timesync values. */
#define OTX2_CYCLECOUNTER_MASK 0xffffffffffffffffULL
+#define OCTEONTX2_PMD net_octeontx2
+
+#define otx2_ethdev_is_same_driver(dev) \
+ (strcmp((dev)->device->driver->name, RTE_STR(OCTEONTX2_PMD)) == 0)
+
enum nix_q_size_e {
nix_q_size_16, /* 16 entries */
nix_q_size_64, /* 64 entries */
enum nix_q_size_e {
nix_q_size_16, /* 16 entries */
nix_q_size_64, /* 64 entries */
@@
-192,6
+205,7
@@
struct otx2_eth_qconf {
void *mempool;
uint32_t socket_id;
uint16_t nb_desc;
void *mempool;
uint32_t socket_id;
uint16_t nb_desc;
+ uint8_t valid;
};
struct otx2_fc_info {
};
struct otx2_fc_info {
@@
-254,7
+268,7
@@
struct otx2_vlan_info {
struct otx2_eth_dev {
OTX2_DEV; /* Base class */
struct otx2_eth_dev {
OTX2_DEV; /* Base class */
- MARKER otx2_eth_dev_data_start;
+
RTE_
MARKER otx2_eth_dev_data_start;
uint16_t sqb_size;
uint16_t rx_chan_base;
uint16_t tx_chan_base;
uint16_t sqb_size;
uint16_t rx_chan_base;
uint16_t tx_chan_base;
@@
-266,8
+280,11
@@
struct otx2_eth_dev {
uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
uint8_t mkex_pfl_name[MKEX_NAME_LEN];
uint8_t max_mac_entries;
uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
uint8_t mkex_pfl_name[MKEX_NAME_LEN];
uint8_t max_mac_entries;
+ bool dmac_filter_enable;
uint8_t lf_tx_stats;
uint8_t lf_rx_stats;
uint8_t lf_tx_stats;
uint8_t lf_rx_stats;
+ uint8_t lock_rx_ctx;
+ uint8_t lock_tx_ctx;
uint16_t flags;
uint16_t cints;
uint16_t qints;
uint16_t flags;
uint16_t cints;
uint16_t qints;
@@
-276,10
+293,12
@@
struct otx2_eth_dev {
uint8_t configured_cints;
uint8_t configured_nb_rx_qs;
uint8_t configured_nb_tx_qs;
uint8_t configured_cints;
uint8_t configured_nb_rx_qs;
uint8_t configured_nb_tx_qs;
+ uint8_t ptype_disable;
uint16_t nix_msixoff;
uintptr_t base;
uintptr_t lmt_addr;
uint16_t scalar_ena;
uint16_t nix_msixoff;
uintptr_t base;
uintptr_t lmt_addr;
uint16_t scalar_ena;
+ uint16_t rss_tag_as_xor;
uint16_t max_sqb_count;
uint16_t rx_offload_flags; /* Selected Rx offload flags(NIX_RX_*_F) */
uint64_t rx_offloads;
uint16_t max_sqb_count;
uint16_t rx_offload_flags; /* Selected Rx offload flags(NIX_RX_*_F) */
uint64_t rx_offloads;
@@
-298,8
+317,10
@@
struct otx2_eth_dev {
/* Contiguous queues */
uint16_t txschq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
uint16_t otx2_tm_root_lvl;
/* Contiguous queues */
uint16_t txschq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
uint16_t otx2_tm_root_lvl;
+ uint16_t link_cfg_lvl;
uint16_t tm_flags;
uint16_t tm_leaf_cnt;
uint16_t tm_flags;
uint16_t tm_leaf_cnt;
+ uint64_t tm_rate_min;
struct otx2_nix_tm_node_list node_list;
struct otx2_nix_tm_shaper_profile_list shaper_profile_list;
struct otx2_rss_info rss_info;
struct otx2_nix_tm_node_list node_list;
struct otx2_nix_tm_shaper_profile_list shaper_profile_list;
struct otx2_rss_info rss_info;
@@
-323,6
+344,10
@@
struct otx2_eth_dev {
bool mc_tbl_set;
struct otx2_nix_mc_filter_tbl mc_fltr_tbl;
bool sdp_link; /* SDP flag */
bool mc_tbl_set;
struct otx2_nix_mc_filter_tbl mc_fltr_tbl;
bool sdp_link; /* SDP flag */
+ /* Inline IPsec params */
+ uint16_t ipsec_in_max_spi;
+ uint8_t duplex;
+ uint32_t speed;
} __rte_cache_aligned;
struct otx2_eth_txq {
} __rte_cache_aligned;
struct otx2_eth_txq {
@@
-334,7
+359,7
@@
struct otx2_eth_txq {
rte_iova_t fc_iova;
uint16_t sqes_per_sqb_log2;
int16_t nb_sqb_bufs_adj;
rte_iova_t fc_iova;
uint16_t sqes_per_sqb_log2;
int16_t nb_sqb_bufs_adj;
- MARKER slow_path_start;
+
RTE_
MARKER slow_path_start;
uint16_t nb_sqb_bufs;
uint16_t sq;
uint64_t offloads;
uint16_t nb_sqb_bufs;
uint16_t sq;
uint64_t offloads;
@@
-356,7
+381,7
@@
struct otx2_eth_rxq {
uint32_t available;
uint16_t rq;
struct otx2_timesync_info *tstamp;
uint32_t available;
uint16_t rq;
struct otx2_timesync_info *tstamp;
- MARKER slow_path_start;
+
RTE_
MARKER slow_path_start;
uint64_t aura;
uint64_t offloads;
uint32_t qlen;
uint64_t aura;
uint64_t offloads;
uint32_t qlen;
@@
-376,9
+401,8
@@
otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev)
/* Ops */
int otx2_nix_info_get(struct rte_eth_dev *eth_dev,
struct rte_eth_dev_info *dev_info);
/* Ops */
int otx2_nix_info_get(struct rte_eth_dev *eth_dev,
struct rte_eth_dev_info *dev_info);
-int otx2_nix_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
- enum rte_filter_type filter_type,
- enum rte_filter_op filter_op, void *arg);
+int otx2_nix_dev_flow_ops_get(struct rte_eth_dev *eth_dev,
+ const struct rte_flow_ops **ops);
int otx2_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
size_t fw_size);
int otx2_nix_get_module_info(struct rte_eth_dev *eth_dev,
int otx2_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
size_t fw_size);
int otx2_nix_get_module_info(struct rte_eth_dev *eth_dev,
@@
-421,6
+445,8
@@
int otx2_nix_set_mc_addr_list(struct rte_eth_dev *eth_dev,
/* MTU */
int otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
int otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev);
/* MTU */
int otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
int otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev);
+void otx2_nix_enable_mseg_on_jumbo(struct otx2_eth_rxq *rxq);
+
/* Link */
void otx2_nix_toggle_flag_link_cfg(struct otx2_eth_dev *dev, bool set);
/* Link */
void otx2_nix_toggle_flag_link_cfg(struct otx2_eth_dev *dev, bool set);
@@
-429,6
+455,7
@@
void otx2_eth_dev_link_status_update(struct otx2_dev *dev,
struct cgx_link_user_info *link);
int otx2_nix_dev_set_link_up(struct rte_eth_dev *eth_dev);
int otx2_nix_dev_set_link_down(struct rte_eth_dev *eth_dev);
struct cgx_link_user_info *link);
int otx2_nix_dev_set_link_up(struct rte_eth_dev *eth_dev);
int otx2_nix_dev_set_link_down(struct rte_eth_dev *eth_dev);
+int otx2_apply_link_speed(struct rte_eth_dev *eth_dev);
/* IRQ */
int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);
/* IRQ */
int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);
@@
-437,6
+464,8
@@
int oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev);
void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);
void oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev);
void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);
void oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev);
+void otx2_nix_err_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);
+void otx2_nix_ras_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);
int otx2_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
uint16_t rx_queue_id);
int otx2_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
uint16_t rx_queue_id);
@@
-449,6
+478,7
@@
int otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
struct rte_dev_reg_info *regs);
int otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev);
void otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);
struct rte_dev_reg_info *regs);
int otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev);
void otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);
+void otx2_nix_tm_dump(struct otx2_eth_dev *dev);
/* Stats */
int otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,
/* Stats */
int otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,
@@
-503,6
+533,8
@@
int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,
struct rte_ether_addr *addr);
/* Flow Control */
struct rte_ether_addr *addr);
/* Flow Control */
+int otx2_nix_flow_ctrl_init(struct rte_eth_dev *eth_dev);
+
int otx2_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
struct rte_eth_fc_conf *fc_conf);
int otx2_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
struct rte_eth_fc_conf *fc_conf);