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net/mlx5: add Altivec Rx
[dpdk.git]
/
drivers
/
net
/
qede
/
base
/
bcm_osal.c
diff --git
a/drivers/net/qede/base/bcm_osal.c
b/drivers/net/qede/base/bcm_osal.c
index
968fb76
..
48d016e
100644
(file)
--- a/
drivers/net/qede/base/bcm_osal.c
+++ b/
drivers/net/qede/base/bcm_osal.c
@@
-1,9
+1,7
@@
-/*
- * Copyright (c) 2016
QLogic Corporation
.
+/*
SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2016
- 2018 Cavium Inc
.
* All rights reserved.
* All rights reserved.
- * www.qlogic.com
- *
- * See LICENSE.qede_pmd for copyright and licensing details.
+ * www.cavium.com
*/
#include <rte_memzone.h>
*/
#include <rte_memzone.h>
@@
-12,6
+10,7
@@
#include "bcm_osal.h"
#include "ecore.h"
#include "ecore_hw.h"
#include "bcm_osal.h"
#include "ecore.h"
#include "ecore_hw.h"
+#include "ecore_dev_api.h"
#include "ecore_iov_api.h"
#include "ecore_mcp_api.h"
#include "ecore_l2_api.h"
#include "ecore_iov_api.h"
#include "ecore_mcp_api.h"
#include "ecore_l2_api.h"
@@
-19,7
+18,7
@@
/* Array of memzone pointers */
static const struct rte_memzone *ecore_mz_mapping[RTE_MAX_MEMZONE];
/* Counter to track current memzone allocated */
/* Array of memzone pointers */
static const struct rte_memzone *ecore_mz_mapping[RTE_MAX_MEMZONE];
/* Counter to track current memzone allocated */
-uint16_t ecore_mz_count;
+
static
uint16_t ecore_mz_count;
unsigned long qede_log2_align(unsigned long n)
{
unsigned long qede_log2_align(unsigned long n)
{
@@
-130,13
+129,13
@@
void *osal_dma_alloc_coherent(struct ecore_dev *p_dev,
}
OSAL_MEM_ZERO(mz_name, sizeof(*mz_name));
}
OSAL_MEM_ZERO(mz_name, sizeof(*mz_name));
- snprintf(mz_name, sizeof(mz_name)
- 1
, "%lx",
+ snprintf(mz_name, sizeof(mz_name), "%lx",
(unsigned long)rte_get_timer_cycles());
if (core_id == (unsigned int)LCORE_ID_ANY)
(unsigned long)rte_get_timer_cycles());
if (core_id == (unsigned int)LCORE_ID_ANY)
- core_id =
0
;
+ core_id =
rte_get_master_lcore()
;
socket_id = rte_lcore_to_socket_id(core_id);
socket_id = rte_lcore_to_socket_id(core_id);
- mz = rte_memzone_reserve_aligned(mz_name, size,
-
socket_id, 0
, RTE_CACHE_LINE_SIZE);
+ mz = rte_memzone_reserve_aligned(mz_name, size,
socket_id,
+
RTE_MEMZONE_IOVA_CONTIG
, RTE_CACHE_LINE_SIZE);
if (!mz) {
DP_ERR(p_dev, "Unable to allocate DMA memory "
"of size %zu bytes - %s\n",
if (!mz) {
DP_ERR(p_dev, "Unable to allocate DMA memory "
"of size %zu bytes - %s\n",
@@
-144,12
+143,12
@@
void *osal_dma_alloc_coherent(struct ecore_dev *p_dev,
*phys = 0;
return OSAL_NULL;
}
*phys = 0;
return OSAL_NULL;
}
- *phys = mz->
phys_addr
;
+ *phys = mz->
iova
;
ecore_mz_mapping[ecore_mz_count++] = mz;
DP_VERBOSE(p_dev, ECORE_MSG_SP,
"Allocated dma memory size=%zu phys=0x%lx"
" virt=%p core=%d\n",
ecore_mz_mapping[ecore_mz_count++] = mz;
DP_VERBOSE(p_dev, ECORE_MSG_SP,
"Allocated dma memory size=%zu phys=0x%lx"
" virt=%p core=%d\n",
- mz->len, (unsigned long)mz->
phys_addr
, mz->addr, core_id);
+ mz->len, (unsigned long)mz->
iova
, mz->addr, core_id);
return mz->addr;
}
return mz->addr;
}
@@
-169,12
+168,13
@@
void *osal_dma_alloc_coherent_aligned(struct ecore_dev *p_dev,
}
OSAL_MEM_ZERO(mz_name, sizeof(*mz_name));
}
OSAL_MEM_ZERO(mz_name, sizeof(*mz_name));
- snprintf(mz_name, sizeof(mz_name)
- 1
, "%lx",
+ snprintf(mz_name, sizeof(mz_name), "%lx",
(unsigned long)rte_get_timer_cycles());
if (core_id == (unsigned int)LCORE_ID_ANY)
(unsigned long)rte_get_timer_cycles());
if (core_id == (unsigned int)LCORE_ID_ANY)
- core_id =
0
;
+ core_id =
rte_get_master_lcore()
;
socket_id = rte_lcore_to_socket_id(core_id);
socket_id = rte_lcore_to_socket_id(core_id);
- mz = rte_memzone_reserve_aligned(mz_name, size, socket_id, 0, align);
+ mz = rte_memzone_reserve_aligned(mz_name, size, socket_id,
+ RTE_MEMZONE_IOVA_CONTIG, align);
if (!mz) {
DP_ERR(p_dev, "Unable to allocate DMA memory "
"of size %zu bytes - %s\n",
if (!mz) {
DP_ERR(p_dev, "Unable to allocate DMA memory "
"of size %zu bytes - %s\n",
@@
-182,12
+182,12
@@
void *osal_dma_alloc_coherent_aligned(struct ecore_dev *p_dev,
*phys = 0;
return OSAL_NULL;
}
*phys = 0;
return OSAL_NULL;
}
- *phys = mz->
phys_addr
;
+ *phys = mz->
iova
;
ecore_mz_mapping[ecore_mz_count++] = mz;
DP_VERBOSE(p_dev, ECORE_MSG_SP,
"Allocated aligned dma memory size=%zu phys=0x%lx"
" virt=%p core=%d\n",
ecore_mz_mapping[ecore_mz_count++] = mz;
DP_VERBOSE(p_dev, ECORE_MSG_SP,
"Allocated aligned dma memory size=%zu phys=0x%lx"
" virt=%p core=%d\n",
- mz->len, (unsigned long)mz->
phys_addr
, mz->addr, core_id);
+ mz->len, (unsigned long)mz->
iova
, mz->addr, core_id);
return mz->addr;
}
return mz->addr;
}
@@
-196,10
+196,15
@@
void osal_dma_free_mem(struct ecore_dev *p_dev, dma_addr_t phys)
uint16_t j;
for (j = 0 ; j < ecore_mz_count; j++) {
uint16_t j;
for (j = 0 ; j < ecore_mz_count; j++) {
- if (phys == ecore_mz_mapping[j]->
phys_addr
) {
+ if (phys == ecore_mz_mapping[j]->
iova
) {
DP_VERBOSE(p_dev, ECORE_MSG_SP,
"Free memzone %s\n", ecore_mz_mapping[j]->name);
rte_memzone_free(ecore_mz_mapping[j]);
DP_VERBOSE(p_dev, ECORE_MSG_SP,
"Free memzone %s\n", ecore_mz_mapping[j]->name);
rte_memzone_free(ecore_mz_mapping[j]);
+ while (j < ecore_mz_count - 1) {
+ ecore_mz_mapping[j] = ecore_mz_mapping[j + 1];
+ j++;
+ }
+ ecore_mz_count--;
return;
}
}
return;
}
}
@@
-249,8
+254,11
@@
qede_get_mcp_proto_stats(struct ecore_dev *edev,
if (type == ECORE_MCP_LAN_STATS) {
ecore_get_vport_stats(edev, &lan_stats);
if (type == ECORE_MCP_LAN_STATS) {
ecore_get_vport_stats(edev, &lan_stats);
- stats->lan_stats.ucast_rx_pkts = lan_stats.rx_ucast_pkts;
- stats->lan_stats.ucast_tx_pkts = lan_stats.tx_ucast_pkts;
+
+ /* @DPDK */
+ stats->lan_stats.ucast_rx_pkts = lan_stats.common.rx_ucast_pkts;
+ stats->lan_stats.ucast_tx_pkts = lan_stats.common.tx_ucast_pkts;
+
stats->lan_stats.fcs_err = -1;
} else {
DP_INFO(edev, "Statistics request type %d not supported\n",
stats->lan_stats.fcs_err = -1;
} else {
DP_INFO(edev, "Statistics request type %d not supported\n",
@@
-289,3
+297,15
@@
qede_hw_err_notify(struct ecore_hwfn *p_hwfn, enum ecore_hw_err_type err_type)
DP_ERR(p_hwfn, "HW error occurred [%s]\n", err_str);
ecore_int_attn_clr_enable(p_hwfn->p_dev, true);
}
DP_ERR(p_hwfn, "HW error occurred [%s]\n", err_str);
ecore_int_attn_clr_enable(p_hwfn->p_dev, true);
}
+
+u32 qede_crc32(u32 crc, u8 *ptr, u32 length)
+{
+ int i;
+
+ while (length--) {
+ crc ^= *ptr++;
+ for (i = 0; i < 8; i++)
+ crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320 : 0);
+ }
+ return crc;
+}