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net/ice: fix firmware version result of ethtool
[dpdk.git]
/
drivers
/
net
/
qede
/
base
/
ecore_gtt_reg_addr.h
diff --git
a/drivers/net/qede/base/ecore_gtt_reg_addr.h
b/drivers/net/qede/base/ecore_gtt_reg_addr.h
index
070588d
..
8c8fed4
100644
(file)
--- a/
drivers/net/qede/base/ecore_gtt_reg_addr.h
+++ b/
drivers/net/qede/base/ecore_gtt_reg_addr.h
@@
-1,52
+1,50
@@
-/*
- * Copyright (c) 2016
QLogic Corporation
.
+/*
SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2016
- 2018 Cavium Inc
.
* All rights reserved.
* All rights reserved.
- * www.qlogic.com
- *
- * See LICENSE.qede_pmd for copyright and licensing details.
+ * www.cavium.com
*/
#ifndef GTT_REG_ADDR_H
#define GTT_REG_ADDR_H
/* Win 2 */
*/
#ifndef GTT_REG_ADDR_H
#define GTT_REG_ADDR_H
/* Win 2 */
-/* Access:RW DataWidth:0x20
Chips: BB_B0 K2 E5
*/
+/* Access:RW DataWidth:0x20 */
#define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL
/* Win 3 */
#define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL
/* Win 3 */
-/* Access:RW DataWidth:0x20
Chips: BB_B0 K2 E5
*/
+/* Access:RW DataWidth:0x20 */
#define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL
/* Win 4 */
#define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL
/* Win 4 */
-/* Access:RW DataWidth:0x20
Chips: BB_B0 K2 E5
*/
+/* Access:RW DataWidth:0x20 */
#define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL
/* Win 5 */
#define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL
/* Win 5 */
-/* Access:RW DataWidth:0x20
Chips: BB_B0 K2 E5
*/
+/* Access:RW DataWidth:0x20 */
#define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL
/* Win 6 */
#define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL
/* Win 6 */
-/* Access:RW DataWidth:0x20
Chips: BB_B0 K2 E5
*/
+/* Access:RW DataWidth:0x20 */
#define GTT_BAR0_MAP_REG_USDM_RAM 0x013000UL
/* Win 7 */
#define GTT_BAR0_MAP_REG_USDM_RAM 0x013000UL
/* Win 7 */
-/* Access:RW DataWidth:0x20
Chips: BB_B0 K2 E5
*/
+/* Access:RW DataWidth:0x20 */
#define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x014000UL
/* Win 8 */
#define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x014000UL
/* Win 8 */
-/* Access:RW DataWidth:0x20
Chips: BB_B0 K2 E5
*/
+/* Access:RW DataWidth:0x20 */
#define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x015000UL
/* Win 9 */
#define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x015000UL
/* Win 9 */
-/* Access:RW DataWidth:0x20
Chips: BB_B0 K2 E5
*/
+/* Access:RW DataWidth:0x20 */
#define GTT_BAR0_MAP_REG_XSDM_RAM 0x016000UL
/* Win 10 */
#define GTT_BAR0_MAP_REG_XSDM_RAM 0x016000UL
/* Win 10 */
-/* Access:RW DataWidth:0x20
Chips: BB_B0 K2 E5
*/
+/* Access:RW DataWidth:0x20 */
#define GTT_BAR0_MAP_REG_YSDM_RAM 0x017000UL
/* Win 11 */
#define GTT_BAR0_MAP_REG_YSDM_RAM 0x017000UL
/* Win 11 */
-/* Access:RW DataWidth:0x20
Chips: BB_B0 K2 E5
*/
+/* Access:RW DataWidth:0x20 */
#define GTT_BAR0_MAP_REG_PSDM_RAM 0x018000UL
#endif
#define GTT_BAR0_MAP_REG_PSDM_RAM 0x018000UL
#endif