+#ifndef ASIC_ONLY
+static void ecore_emul_mcp_load_req(struct ecore_hwfn *p_hwfn,
+ struct ecore_mcp_mb_params *p_mb_params)
+{
+ if (GET_MFW_FIELD(p_mb_params->param, DRV_ID_MCP_HSI_VER) !=
+ 1 /* ECORE_LOAD_REQ_HSI_VER_1 */) {
+ p_mb_params->mcp_resp = FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1;
+ return;
+ }
+
+ if (!loaded)
+ p_mb_params->mcp_resp = FW_MSG_CODE_DRV_LOAD_ENGINE;
+ else if (!loaded_port[p_hwfn->port_id])
+ p_mb_params->mcp_resp = FW_MSG_CODE_DRV_LOAD_PORT;
+ else
+ p_mb_params->mcp_resp = FW_MSG_CODE_DRV_LOAD_FUNCTION;
+
+ /* On CMT, always tell that it's engine */
+ if (ECORE_IS_CMT(p_hwfn->p_dev))
+ p_mb_params->mcp_resp = FW_MSG_CODE_DRV_LOAD_ENGINE;
+
+ loaded++;
+ loaded_port[p_hwfn->port_id]++;
+
+ DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
+ "Load phase: 0x%08x load cnt: 0x%x port id=%d port_load=%d\n",
+ p_mb_params->mcp_resp, loaded, p_hwfn->port_id,
+ loaded_port[p_hwfn->port_id]);
+}
+
+static void ecore_emul_mcp_unload_req(struct ecore_hwfn *p_hwfn)
+{
+ loaded--;
+ loaded_port[p_hwfn->port_id]--;
+ DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n", loaded);
+}
+
+static enum _ecore_status_t
+ecore_emul_mcp_cmd(struct ecore_hwfn *p_hwfn,
+ struct ecore_mcp_mb_params *p_mb_params)
+{
+ if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev))
+ return ECORE_INVAL;
+
+ switch (p_mb_params->cmd) {
+ case DRV_MSG_CODE_LOAD_REQ:
+ ecore_emul_mcp_load_req(p_hwfn, p_mb_params);
+ break;
+ case DRV_MSG_CODE_UNLOAD_REQ:
+ ecore_emul_mcp_unload_req(p_hwfn);
+ break;
+ case DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT:
+ case DRV_MSG_CODE_RESOURCE_CMD:
+ case DRV_MSG_CODE_MDUMP_CMD:
+ case DRV_MSG_CODE_GET_ENGINE_CONFIG:
+ case DRV_MSG_CODE_GET_PPFID_BITMAP:
+ return ECORE_NOTIMPL;
+ default:
+ break;
+ }
+
+ return ECORE_SUCCESS;
+}
+#endif
+