+ /* Select the number of allowed port link in aux power */
+ #define NVM_CFG1_GLOB_NCSI_AUX_LINK_MASK 0x00000300
+ #define NVM_CFG1_GLOB_NCSI_AUX_LINK_OFFSET 8
+ #define NVM_CFG1_GLOB_NCSI_AUX_LINK_DEFAULT 0x0
+ #define NVM_CFG1_GLOB_NCSI_AUX_LINK_1_PORT 0x1
+ #define NVM_CFG1_GLOB_NCSI_AUX_LINK_2_PORTS 0x2
+ #define NVM_CFG1_GLOB_NCSI_AUX_LINK_3_PORTS 0x3
+ /* Set Trace Filter Log Level */
+ #define NVM_CFG1_GLOB_TRACE_LEVEL_MASK 0x00000C00
+ #define NVM_CFG1_GLOB_TRACE_LEVEL_OFFSET 10
+ #define NVM_CFG1_GLOB_TRACE_LEVEL_ALL 0x0
+ #define NVM_CFG1_GLOB_TRACE_LEVEL_DEBUG 0x1
+ #define NVM_CFG1_GLOB_TRACE_LEVEL_TRACE 0x2
+ #define NVM_CFG1_GLOB_TRACE_LEVEL_ERROR 0x3
+ /* For OCP2.0, MFW listens on SMBUS slave address 0x3e, and return
+ * temperature reading
+ */
+ #define NVM_CFG1_GLOB_EMULATED_TMP421_MASK 0x00001000
+ #define NVM_CFG1_GLOB_EMULATED_TMP421_OFFSET 12
+ #define NVM_CFG1_GLOB_EMULATED_TMP421_DISABLED 0x0
+ #define NVM_CFG1_GLOB_EMULATED_TMP421_ENABLED 0x1
+ /* GPIO which triggers when ASIC temperature reaches nvm option 286
+ * value
+ */
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_MASK 0x001FE000
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_OFFSET 13
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_NA 0x0
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO0 0x1
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO1 0x2
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO2 0x3
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO3 0x4
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO4 0x5
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO5 0x6
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO6 0x7
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO7 0x8
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO8 0x9
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO9 0xA
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO10 0xB
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO11 0xC
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO12 0xD
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO13 0xE
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO14 0xF
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO15 0x10
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO16 0x11
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO17 0x12
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO18 0x13
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO19 0x14
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO20 0x15
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO21 0x16
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO22 0x17
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO23 0x18
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO24 0x19
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO25 0x1A
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO26 0x1B
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO27 0x1C
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO28 0x1D
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO29 0x1E
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO30 0x1F
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO31 0x20
+ /* Warning temperature threshold used with nvm option 286 */
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_THRESHOLD_MASK 0x1FE00000
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_THRESHOLD_OFFSET 21
+ /* Disable PLDM protocol */
+ #define NVM_CFG1_GLOB_DISABLE_PLDM_MASK 0x20000000
+ #define NVM_CFG1_GLOB_DISABLE_PLDM_OFFSET 29
+ #define NVM_CFG1_GLOB_DISABLE_PLDM_DISABLED 0x0
+ #define NVM_CFG1_GLOB_DISABLE_PLDM_ENABLED 0x1
+ /* Disable OCBB protocol */
+ #define NVM_CFG1_GLOB_DISABLE_MCTP_OEM_MASK 0x40000000
+ #define NVM_CFG1_GLOB_DISABLE_MCTP_OEM_OFFSET 30
+ #define NVM_CFG1_GLOB_DISABLE_MCTP_OEM_DISABLED 0x0
+ #define NVM_CFG1_GLOB_DISABLE_MCTP_OEM_ENABLED 0x1
+ u32 preboot_debug_mode_std; /* 0x140 */
+ u32 preboot_debug_mode_ext; /* 0x144 */
+ u32 ext_phy_cfg1; /* 0x148 */
+ /* Ext PHY MDI pair swap value */
+ #define NVM_CFG1_GLOB_RESERVED_244_MASK 0x0000FFFF
+ #define NVM_CFG1_GLOB_RESERVED_244_OFFSET 0
+ /* Define for PGOOD signal Mapping for EXT PHY */
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_MASK 0x00FF0000
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_OFFSET 16
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_NA 0x0
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO0 0x1
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO1 0x2
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO2 0x3
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO3 0x4
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO4 0x5
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO5 0x6
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO6 0x7
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO7 0x8
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO8 0x9
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO9 0xA
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO10 0xB
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO11 0xC
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO12 0xD
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO13 0xE
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO14 0xF
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO15 0x10
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO16 0x11
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO17 0x12
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO18 0x13
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO19 0x14
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO20 0x15
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO21 0x16
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO22 0x17
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO23 0x18
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO24 0x19
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO25 0x1A
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO26 0x1B
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO27 0x1C
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO28 0x1D
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO29 0x1E
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO30 0x1F
+ #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO31 0x20
+ /* GPIO which trigger when PERST asserted */
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_MASK 0xFF000000
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_OFFSET 24
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_NA 0x0
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO0 0x1
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO1 0x2
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO2 0x3
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO3 0x4
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO4 0x5
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO5 0x6
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO6 0x7
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO7 0x8
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO8 0x9
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO9 0xA
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO10 0xB
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO11 0xC
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO12 0xD
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO13 0xE
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO14 0xF
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO15 0x10
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO16 0x11
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO17 0x12
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO18 0x13
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO19 0x14
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO20 0x15
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO21 0x16
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO22 0x17
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO23 0x18
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO24 0x19
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO25 0x1A
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO26 0x1B
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO27 0x1C
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO28 0x1D
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO29 0x1E
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO30 0x1F
+ #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO31 0x20
+ u32 clocks; /* 0x14C */
+ /* Sets core clock frequency */
+ #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MASK 0x000000FF
+ #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_OFFSET 0
+ #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_DEFAULT 0x0
+ #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_375 0x1
+ #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_350 0x2
+ #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_325 0x3
+ #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_300 0x4
+ #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_280 0x5
+ /* Sets MAC clock frequency */
+ #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MASK 0x0000FF00
+ #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_OFFSET 8
+ #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MAC_CLK_DEFAULT 0x0
+ #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MAC_CLK_782 0x1
+ #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MAC_CLK_516 0x2
+ /* Sets storm clock frequency */
+ #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_MASK 0x00FF0000
+ #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_OFFSET 16
+ #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_DEFAULT 0x0
+ #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_1200 0x1
+ #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_1000 0x2
+ #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_900 0x3
+ #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_1100 0x4
+ /* Non zero value will override PCIe AGC threshold to improve
+ * receiver
+ */
+ #define NVM_CFG1_GLOB_OVERRIDE_AGC_THRESHOLD_MASK 0xFF000000
+ #define NVM_CFG1_GLOB_OVERRIDE_AGC_THRESHOLD_OFFSET 24
+ u32 pre2_generic_cont_1; /* 0x150 */
+ #define NVM_CFG1_GLOB_50G_HLPC_PRE2_MASK 0x000000FF
+ #define NVM_CFG1_GLOB_50G_HLPC_PRE2_OFFSET 0
+ #define NVM_CFG1_GLOB_50G_MLPC_PRE2_MASK 0x0000FF00
+ #define NVM_CFG1_GLOB_50G_MLPC_PRE2_OFFSET 8
+ #define NVM_CFG1_GLOB_50G_LLPC_PRE2_MASK 0x00FF0000
+ #define NVM_CFG1_GLOB_50G_LLPC_PRE2_OFFSET 16
+ #define NVM_CFG1_GLOB_25G_HLPC_PRE2_MASK 0xFF000000
+ #define NVM_CFG1_GLOB_25G_HLPC_PRE2_OFFSET 24
+ u32 pre2_generic_cont_2; /* 0x154 */
+ #define NVM_CFG1_GLOB_25G_LLPC_PRE2_MASK 0x000000FF
+ #define NVM_CFG1_GLOB_25G_LLPC_PRE2_OFFSET 0
+ #define NVM_CFG1_GLOB_25G_AC_PRE2_MASK 0x0000FF00
+ #define NVM_CFG1_GLOB_25G_AC_PRE2_OFFSET 8
+ #define NVM_CFG1_GLOB_10G_PC_PRE2_MASK 0x00FF0000
+ #define NVM_CFG1_GLOB_10G_PC_PRE2_OFFSET 16
+ #define NVM_CFG1_GLOB_PRE2_10G_AC_MASK 0xFF000000
+ #define NVM_CFG1_GLOB_PRE2_10G_AC_OFFSET 24
+ u32 pre2_generic_cont_3; /* 0x158 */
+ #define NVM_CFG1_GLOB_1G_PRE2_MASK 0x000000FF
+ #define NVM_CFG1_GLOB_1G_PRE2_OFFSET 0
+ #define NVM_CFG1_GLOB_5G_BT_PRE2_MASK 0x0000FF00
+ #define NVM_CFG1_GLOB_5G_BT_PRE2_OFFSET 8
+ #define NVM_CFG1_GLOB_10G_BT_PRE2_MASK 0x00FF0000
+ #define NVM_CFG1_GLOB_10G_BT_PRE2_OFFSET 16
+ /* When temperature goes below (warning temperature - delta) warning
+ * gpio is unset
+ */
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_DELTA_MASK 0xFF000000
+ #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_DELTA_OFFSET 24
+ u32 tx_rx_eq_50g_hlpc; /* 0x15C */
+ #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_HLPC_MASK 0x000000FF
+ #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_HLPC_OFFSET 0
+ #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_HLPC_MASK 0x0000FF00
+ #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_HLPC_OFFSET 8
+ #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_HLPC_MASK 0x00FF0000
+ #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_HLPC_OFFSET 16
+ #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_HLPC_MASK 0xFF000000
+ #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_HLPC_OFFSET 24
+ u32 tx_rx_eq_50g_mlpc; /* 0x160 */
+ #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_MLPC_MASK 0x000000FF
+ #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_MLPC_OFFSET 0
+ #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_MLPC_MASK 0x0000FF00
+ #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_MLPC_OFFSET 8
+ #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_MLPC_MASK 0x00FF0000
+ #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_MLPC_OFFSET 16
+ #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_MLPC_MASK 0xFF000000
+ #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_MLPC_OFFSET 24
+ u32 tx_rx_eq_50g_llpc; /* 0x164 */
+ #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_LLPC_MASK 0x000000FF
+ #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_LLPC_OFFSET 0
+ #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_LLPC_MASK 0x0000FF00
+ #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_LLPC_OFFSET 8
+ #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_LLPC_MASK 0x00FF0000
+ #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_LLPC_OFFSET 16
+ #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_LLPC_MASK 0xFF000000
+ #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_LLPC_OFFSET 24
+ u32 tx_rx_eq_50g_ac; /* 0x168 */
+ #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_AC_MASK 0x000000FF
+ #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_AC_OFFSET 0
+ #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_AC_MASK 0x0000FF00
+ #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_AC_OFFSET 8
+ #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_AC_MASK 0x00FF0000
+ #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_AC_OFFSET 16
+ #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_AC_MASK 0xFF000000
+ #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_AC_OFFSET 24
+ /* Set Trace Filter Modules Log Bit Mask */
+ u32 trace_modules; /* 0x16C */
+ #define NVM_CFG1_GLOB_TRACE_MODULES_ERROR 0x1
+ #define NVM_CFG1_GLOB_TRACE_MODULES_DBG 0x2
+ #define NVM_CFG1_GLOB_TRACE_MODULES_DRV_HSI 0x4
+ #define NVM_CFG1_GLOB_TRACE_MODULES_INTERRUPT 0x8
+ #define NVM_CFG1_GLOB_TRACE_MODULES_VPD 0x10
+ #define NVM_CFG1_GLOB_TRACE_MODULES_FLR 0x20
+ #define NVM_CFG1_GLOB_TRACE_MODULES_INIT 0x40
+ #define NVM_CFG1_GLOB_TRACE_MODULES_NVM 0x80
+ #define NVM_CFG1_GLOB_TRACE_MODULES_PIM 0x100
+ #define NVM_CFG1_GLOB_TRACE_MODULES_NET 0x200
+ #define NVM_CFG1_GLOB_TRACE_MODULES_POWER 0x400
+ #define NVM_CFG1_GLOB_TRACE_MODULES_UTILS 0x800
+ #define NVM_CFG1_GLOB_TRACE_MODULES_RESOURCES 0x1000
+ #define NVM_CFG1_GLOB_TRACE_MODULES_SCHEDULER 0x2000
+ #define NVM_CFG1_GLOB_TRACE_MODULES_PHYMOD 0x4000
+ #define NVM_CFG1_GLOB_TRACE_MODULES_EVENTS 0x8000
+ #define NVM_CFG1_GLOB_TRACE_MODULES_PMM 0x10000
+ #define NVM_CFG1_GLOB_TRACE_MODULES_DBG_DRV 0x20000
+ #define NVM_CFG1_GLOB_TRACE_MODULES_ETH 0x40000
+ #define NVM_CFG1_GLOB_TRACE_MODULES_SECURITY 0x80000
+ #define NVM_CFG1_GLOB_TRACE_MODULES_PCIE 0x100000
+ #define NVM_CFG1_GLOB_TRACE_MODULES_TRACE 0x200000
+ #define NVM_CFG1_GLOB_TRACE_MODULES_MANAGEMENT 0x400000
+ #define NVM_CFG1_GLOB_TRACE_MODULES_SIM 0x800000
+ u32 pcie_class_code_fcoe; /* 0x170 */
+ /* Set PCIe FCoE Class Code */
+ #define NVM_CFG1_GLOB_PCIE_CLASS_CODE_FCOE_MASK 0x00FFFFFF
+ #define NVM_CFG1_GLOB_PCIE_CLASS_CODE_FCOE_OFFSET 0
+ /* When temperature goes below (ALOM FAN ON AUX value - delta) ALOM
+ * FAN ON AUX gpio is unset
+ */
+ #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_DELTA_MASK 0xFF000000
+ #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_DELTA_OFFSET 24
+ u32 pcie_class_code_iscsi; /* 0x174 */
+ /* Set PCIe iSCSI Class Code */
+ #define NVM_CFG1_GLOB_PCIE_CLASS_CODE_ISCSI_MASK 0x00FFFFFF
+ #define NVM_CFG1_GLOB_PCIE_CLASS_CODE_ISCSI_OFFSET 0
+ /* When temperature goes below (Dead Temp TH - delta)Thermal Event
+ * gpio is unset
+ */
+ #define NVM_CFG1_GLOB_DEAD_TEMP_TH_DELTA_MASK 0xFF000000
+ #define NVM_CFG1_GLOB_DEAD_TEMP_TH_DELTA_OFFSET 24
+ u32 no_provisioned_mac; /* 0x178 */
+ /* Set number of provisioned MAC addresses */
+ #define NVM_CFG1_GLOB_NUMBER_OF_PROVISIONED_MAC_MASK 0x0000FFFF
+ #define NVM_CFG1_GLOB_NUMBER_OF_PROVISIONED_MAC_OFFSET 0
+ /* Set number of provisioned VF MAC addresses */
+ #define NVM_CFG1_GLOB_NUMBER_OF_PROVISIONED_VF_MAC_MASK 0x00FF0000
+ #define NVM_CFG1_GLOB_NUMBER_OF_PROVISIONED_VF_MAC_OFFSET 16
+ /* Enable/Disable BMC MAC */
+ #define NVM_CFG1_GLOB_PROVISIONED_BMC_MAC_MASK 0x01000000
+ #define NVM_CFG1_GLOB_PROVISIONED_BMC_MAC_OFFSET 24
+ #define NVM_CFG1_GLOB_PROVISIONED_BMC_MAC_DISABLED 0x0
+ #define NVM_CFG1_GLOB_PROVISIONED_BMC_MAC_ENABLED 0x1
+ u32 reserved[43]; /* 0x17C */