+ #define NVM_CFG1_PORT_TX_DISABLE_MASK 0x0000FF00
+ #define NVM_CFG1_PORT_TX_DISABLE_OFFSET 8
+ #define NVM_CFG1_PORT_TX_DISABLE_NA 0x0
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO0 0x1
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO1 0x2
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO2 0x3
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO3 0x4
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO4 0x5
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO5 0x6
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO6 0x7
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO7 0x8
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO8 0x9
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO9 0xA
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO10 0xB
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO11 0xC
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO12 0xD
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO13 0xE
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO14 0xF
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO15 0x10
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO16 0x11
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO17 0x12
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO18 0x13
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO19 0x14
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO20 0x15
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO21 0x16
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO22 0x17
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO23 0x18
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO24 0x19
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO25 0x1A
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO26 0x1B
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO27 0x1C
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO28 0x1D
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO29 0x1E
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO30 0x1F
+ #define NVM_CFG1_PORT_TX_DISABLE_GPIO31 0x20
+ u32 mnm_10g_cap; /* 0x4C */
+ #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_MASK \
+ 0x0000FFFF
+ #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
+ #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
+ #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
+ #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_20G 0x4
+ #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
+ #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
+ #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
+ #define \
+ NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
+ #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_MASK \
+ 0xFFFF0000
+ #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
+ 16
+ #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
+ #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
+ #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_20G 0x4
+ #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
+ #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
+ #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
+ #define \
+ NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
+ u32 mnm_10g_ctrl; /* 0x50 */
+ #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_MASK 0x0000000F
+ #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_OFFSET 0
+ #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_AUTONEG 0x0
+ #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_1G 0x1
+ #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_10G 0x2
+ #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_20G 0x3
+ #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_25G 0x4
+ #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_40G 0x5
+ #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_50G 0x6
+ #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_BB_100G 0x7
+ #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_MASK 0x000000F0
+ #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_OFFSET 4
+ #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_AUTONEG 0x0
+ #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_1G 0x1
+ #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_10G 0x2
+ #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_20G 0x3
+ #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_25G 0x4
+ #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_40G 0x5
+ #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_50G 0x6
+ #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_BB_100G 0x7
+ /* This field defines the board technology
+ * (backpane,transceiver,external PHY)
+ */
+ #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MASK 0x0000FF00
+ #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_OFFSET 8
+ #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_UNDEFINED 0x0
+ #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE 0x1
+ #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_BACKPLANE 0x2
+ #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_EXT_PHY 0x3
+ #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE_SLAVE 0x4
+ #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_MASK \
+ 0x00FF0000
+ #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_OFFSET 16
+ #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_BYPASS 0x0
+ #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR 0x2
+ #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR2 0x3
+ #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR4 0x4
+ #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XFI 0x8
+ #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SFI 0x9
+ #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_1000X 0xB
+ #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SGMII 0xC
+ #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLAUI 0x11
+ #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLPPI 0x12
+ #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CAUI 0x21
+ #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CPPI 0x22
+ #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_25GAUI 0x31
+ #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_MASK 0xFF000000
+ #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_OFFSET 24
+ u32 mnm_10g_misc; /* 0x54 */
+ #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_MASK 0x00000007
+ #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_OFFSET 0
+ #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_NONE 0x0
+ #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_FIRECODE 0x1
+ #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_RS 0x2
+ #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_AUTO 0x7
+ u32 mnm_25g_cap; /* 0x58 */
+ #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_MASK \
+ 0x0000FFFF
+ #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
+ #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
+ #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
+ #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_20G 0x4
+ #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
+ #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
+ #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
+ #define \
+ NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
+ #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_MASK \
+ 0xFFFF0000
+ #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
+ 16
+ #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
+ #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
+ #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_20G 0x4
+ #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
+ #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
+ #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
+ #define \
+ NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
+ u32 mnm_25g_ctrl; /* 0x5C */
+ #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_MASK 0x0000000F
+ #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_OFFSET 0
+ #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_AUTONEG 0x0
+ #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_1G 0x1
+ #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_10G 0x2
+ #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_20G 0x3
+ #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_25G 0x4
+ #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_40G 0x5
+ #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_50G 0x6
+ #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_BB_100G 0x7
+ #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_MASK 0x000000F0
+ #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_OFFSET 4
+ #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_AUTONEG 0x0
+ #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_1G 0x1
+ #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_10G 0x2
+ #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_20G 0x3
+ #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_25G 0x4
+ #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_40G 0x5
+ #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_50G 0x6
+ #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_BB_100G 0x7
+ /* This field defines the board technology
+ * (backpane,transceiver,external PHY)
+ */
+ #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MASK 0x0000FF00
+ #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_OFFSET 8
+ #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_UNDEFINED 0x0
+ #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE 0x1
+ #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_BACKPLANE 0x2
+ #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_EXT_PHY 0x3
+ #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE_SLAVE 0x4
+ #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_MASK \
+ 0x00FF0000
+ #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_OFFSET 16
+ #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_BYPASS 0x0
+ #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR 0x2
+ #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR2 0x3
+ #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR4 0x4
+ #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XFI 0x8
+ #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SFI 0x9
+ #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_1000X 0xB
+ #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SGMII 0xC
+ #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLAUI 0x11
+ #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLPPI 0x12
+ #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CAUI 0x21
+ #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CPPI 0x22
+ #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_25GAUI 0x31
+ #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_MASK 0xFF000000
+ #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_OFFSET 24
+ u32 mnm_25g_misc; /* 0x60 */
+ #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_MASK 0x00000007
+ #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_OFFSET 0
+ #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_NONE 0x0
+ #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_FIRECODE 0x1
+ #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_RS 0x2
+ #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_AUTO 0x7
+ u32 mnm_40g_cap; /* 0x64 */
+ #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_MASK \
+ 0x0000FFFF
+ #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
+ #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
+ #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
+ #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_20G 0x4
+ #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
+ #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
+ #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
+ #define \
+ NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
+ #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_MASK \
+ 0xFFFF0000
+ #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
+ 16
+ #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
+ #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
+ #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_20G 0x4
+ #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
+ #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
+ #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
+ #define \
+ NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
+ u32 mnm_40g_ctrl; /* 0x68 */
+ #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_MASK 0x0000000F
+ #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_OFFSET 0
+ #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_AUTONEG 0x0
+ #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_1G 0x1
+ #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_10G 0x2
+ #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_20G 0x3
+ #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_25G 0x4
+ #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_40G 0x5
+ #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_50G 0x6
+ #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_BB_100G 0x7
+ #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_MASK 0x000000F0
+ #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_OFFSET 4
+ #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_AUTONEG 0x0
+ #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_1G 0x1
+ #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_10G 0x2
+ #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_20G 0x3
+ #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_25G 0x4
+ #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_40G 0x5
+ #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_50G 0x6
+ #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_BB_100G 0x7
+ /* This field defines the board technology
+ * (backpane,transceiver,external PHY)
+ */
+ #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MASK 0x0000FF00
+ #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_OFFSET 8
+ #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_UNDEFINED 0x0
+ #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE 0x1
+ #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_BACKPLANE 0x2
+ #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_EXT_PHY 0x3
+ #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE_SLAVE 0x4
+ #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_MASK \
+ 0x00FF0000
+ #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_OFFSET 16
+ #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_BYPASS 0x0
+ #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR 0x2
+ #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR2 0x3
+ #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR4 0x4
+ #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XFI 0x8
+ #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SFI 0x9
+ #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_1000X 0xB
+ #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SGMII 0xC
+ #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLAUI 0x11
+ #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLPPI 0x12
+ #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CAUI 0x21
+ #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CPPI 0x22
+ #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_25GAUI 0x31
+ #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_MASK 0xFF000000
+ #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_OFFSET 24
+ u32 mnm_40g_misc; /* 0x6C */
+ #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_MASK 0x00000007
+ #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_OFFSET 0
+ #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_NONE 0x0
+ #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_FIRECODE 0x1
+ #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_RS 0x2
+ #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_AUTO 0x7
+ u32 mnm_50g_cap; /* 0x70 */
+ #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_MASK \
+ 0x0000FFFF
+ #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
+ #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
+ #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
+ #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_20G 0x4
+ #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
+ #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
+ #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
+ #define \
+ NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_BB_100G \
+ 0x40
+ #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_MASK \
+ 0xFFFF0000
+ #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
+ 16
+ #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
+ #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
+ #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_20G 0x4
+ #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
+ #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
+ #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
+ #define \
+ NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_BB_100G \
+ 0x40
+ u32 mnm_50g_ctrl; /* 0x74 */
+ #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_MASK 0x0000000F
+ #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_OFFSET 0
+ #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_AUTONEG 0x0
+ #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_1G 0x1
+ #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_10G 0x2
+ #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_20G 0x3
+ #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_25G 0x4
+ #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_40G 0x5
+ #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_50G 0x6
+ #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_BB_100G 0x7
+ #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_MASK 0x000000F0
+ #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_OFFSET 4
+ #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_AUTONEG 0x0
+ #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_1G 0x1
+ #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_10G 0x2
+ #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_20G 0x3
+ #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_25G 0x4
+ #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_40G 0x5
+ #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_50G 0x6
+ #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_BB_100G 0x7
+ /* This field defines the board technology
+ * (backpane,transceiver,external PHY)
+ */
+ #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MASK 0x0000FF00
+ #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_OFFSET 8
+ #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_UNDEFINED 0x0
+ #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE 0x1
+ #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_BACKPLANE 0x2
+ #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_EXT_PHY 0x3
+ #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE_SLAVE 0x4
+ #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_MASK \
+ 0x00FF0000
+ #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_OFFSET 16
+ #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_BYPASS 0x0
+ #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR 0x2
+ #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR2 0x3
+ #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR4 0x4
+ #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XFI 0x8
+ #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SFI 0x9
+ #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_1000X 0xB
+ #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SGMII 0xC
+ #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLAUI 0x11
+ #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLPPI 0x12
+ #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CAUI 0x21
+ #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CPPI 0x22
+ #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_25GAUI 0x31
+ #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_MASK 0xFF000000
+ #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_OFFSET 24
+ u32 mnm_50g_misc; /* 0x78 */
+ #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_MASK 0x00000007
+ #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_OFFSET 0
+ #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_NONE 0x0
+ #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_FIRECODE 0x1
+ #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_RS 0x2
+ #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_AUTO 0x7
+ u32 mnm_100g_cap; /* 0x7C */
+ #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_MASK \
+ 0x0000FFFF
+ #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_OFFSET 0
+ #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_1G 0x1
+ #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_10G 0x2
+ #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_20G 0x4
+ #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_25G 0x8
+ #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_40G 0x10
+ #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_50G 0x20
+ #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_BB_100G 0x40
+ #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_MASK \
+ 0xFFFF0000
+ #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_OFFSET 16
+ #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_1G 0x1
+ #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_10G 0x2
+ #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_20G 0x4
+ #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_25G 0x8
+ #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_40G 0x10
+ #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_50G 0x20
+ #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_BB_100G 0x40
+ u32 mnm_100g_ctrl; /* 0x80 */
+ #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_MASK 0x0000000F
+ #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_OFFSET 0
+ #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_AUTONEG 0x0
+ #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_1G 0x1
+ #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_10G 0x2
+ #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_20G 0x3
+ #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_25G 0x4
+ #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_40G 0x5
+ #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_50G 0x6
+ #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_BB_100G 0x7
+ #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_MASK 0x000000F0
+ #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_OFFSET 4
+ #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_AUTONEG 0x0
+ #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_1G 0x1
+ #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_10G 0x2
+ #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_20G 0x3
+ #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_25G 0x4
+ #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_40G 0x5
+ #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_50G 0x6
+ #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_BB_100G 0x7
+ /* This field defines the board technology
+ * (backpane,transceiver,external PHY)
+ */
+ #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MASK 0x0000FF00
+ #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_OFFSET 8
+ #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_UNDEFINED 0x0
+ #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE 0x1
+ #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_BACKPLANE 0x2
+ #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_EXT_PHY 0x3
+ #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE_SLAVE 0x4
+ #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_MASK \
+ 0x00FF0000
+ #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_OFFSET 16
+ #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_BYPASS 0x0
+ #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR 0x2
+ #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR2 0x3
+ #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR4 0x4
+ #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XFI 0x8
+ #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SFI 0x9
+ #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_1000X 0xB
+ #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SGMII 0xC
+ #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLAUI 0x11
+ #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLPPI 0x12
+ #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CAUI 0x21
+ #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CPPI 0x22
+ #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_25GAUI 0x31
+ #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_MASK 0xFF000000
+ #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_OFFSET 24
+ u32 mnm_100g_misc; /* 0x84 */
+ #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_MASK 0x00000007
+ #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_OFFSET 0
+ #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_NONE 0x0
+ #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_FIRECODE 0x1
+ #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_RS 0x2
+ #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_AUTO 0x7
+ u32 temperature; /* 0x88 */
+ #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_MASK 0x000000FF
+ #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_OFFSET 0
+ #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_MASK \
+ 0x0000FF00
+ #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_OFFSET 8
+ /* Warning temperature threshold used with nvm option 235 */
+ #define NVM_CFG1_PORT_PHY_MODULE_WARNING_TEMP_TH_MASK 0x00FF0000
+ #define NVM_CFG1_PORT_PHY_MODULE_WARNING_TEMP_TH_OFFSET 16
+ u32 ext_phy_cfg1; /* 0x8C */
+ /* Ext PHY MDI pair swap value */
+ #define NVM_CFG1_PORT_EXT_PHY_MDI_PAIR_SWAP_MASK 0x0000FFFF
+ #define NVM_CFG1_PORT_EXT_PHY_MDI_PAIR_SWAP_OFFSET 0
+ u32 extended_speed; /* 0x90 */
+ /* Sets speed in conjunction with legacy speed field */
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_MASK 0x0000FFFF
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_OFFSET 0
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_NONE 0x1
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_1G 0x2
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_10G 0x4
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_25G 0x8
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_40G 0x10
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R 0x20
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R2 0x40
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R2 0x80
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R4 0x100
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_P4 0x200
+ /* Sets speed capabilities in conjunction with legacy capabilities
+ * field
+ */
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_MASK 0xFFFF0000
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_OFFSET 16
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_NONE 0x1
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_1G 0x2
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_10G 0x4
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_25G 0x8
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_40G 0x10
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R 0x20
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R2 0x40
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R2 0x80
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R4 0x100
+ #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_P4 0x200
+ /* Set speed specific FEC setting in conjunction with legacy FEC
+ * mode
+ */
+ u32 extended_fec_mode; /* 0x94 */
+ #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_NONE 0x1
+ #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_10G_NONE 0x2
+ #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_10G_BASE_R 0x4
+ #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_25G_NONE 0x8
+ #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_25G_BASE_R 0x10
+ #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_25G_RS528 0x20
+ #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_40G_NONE 0x40
+ #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_40G_BASE_R 0x80
+ #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_50G_NONE 0x100
+ #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_50G_BASE_R 0x200
+ #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_50G_RS528 0x400
+ #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_50G_RS544 0x800
+ #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_100G_NONE 0x1000
+ #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_100G_BASE_R 0x2000
+ #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_100G_RS528 0x4000
+ #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_100G_RS544 0x8000
+ u32 port_generic_cont_01; /* 0x98 */
+ /* Define for GPIO mapping of SFP Rate Select 0 */
+ #define NVM_CFG1_PORT_MODULE_RS0_MASK 0x000000FF
+ #define NVM_CFG1_PORT_MODULE_RS0_OFFSET 0
+ #define NVM_CFG1_PORT_MODULE_RS0_NA 0x0
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO0 0x1
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO1 0x2
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO2 0x3
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO3 0x4
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO4 0x5
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO5 0x6
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO6 0x7
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO7 0x8
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO8 0x9
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO9 0xA
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO10 0xB
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO11 0xC
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO12 0xD
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO13 0xE
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO14 0xF
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO15 0x10
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO16 0x11
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO17 0x12
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO18 0x13
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO19 0x14
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO20 0x15
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO21 0x16
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO22 0x17
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO23 0x18
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO24 0x19
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO25 0x1A
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO26 0x1B
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO27 0x1C
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO28 0x1D
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO29 0x1E
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO30 0x1F
+ #define NVM_CFG1_PORT_MODULE_RS0_GPIO31 0x20
+ /* Define for GPIO mapping of SFP Rate Select 1 */
+ #define NVM_CFG1_PORT_MODULE_RS1_MASK 0x0000FF00
+ #define NVM_CFG1_PORT_MODULE_RS1_OFFSET 8
+ #define NVM_CFG1_PORT_MODULE_RS1_NA 0x0
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO0 0x1
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO1 0x2
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO2 0x3
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO3 0x4
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO4 0x5
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO5 0x6
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO6 0x7
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO7 0x8
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO8 0x9
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO9 0xA
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO10 0xB
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO11 0xC
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO12 0xD
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO13 0xE
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO14 0xF
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO15 0x10
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO16 0x11
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO17 0x12
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO18 0x13
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO19 0x14
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO20 0x15
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO21 0x16
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO22 0x17
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO23 0x18
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO24 0x19
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO25 0x1A
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO26 0x1B
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO27 0x1C
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO28 0x1D
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO29 0x1E
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO30 0x1F
+ #define NVM_CFG1_PORT_MODULE_RS1_GPIO31 0x20
+ /* Define for GPIO mapping of SFP Module TX Fault */
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_MASK 0x00FF0000
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_OFFSET 16
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_NA 0x0
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO0 0x1
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO1 0x2
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO2 0x3
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO3 0x4
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO4 0x5
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO5 0x6
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO6 0x7
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO7 0x8
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO8 0x9
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO9 0xA
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO10 0xB
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO11 0xC
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO12 0xD
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO13 0xE
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO14 0xF
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO15 0x10
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO16 0x11
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO17 0x12
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO18 0x13
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO19 0x14
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO20 0x15
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO21 0x16
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO22 0x17
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO23 0x18
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO24 0x19
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO25 0x1A
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO26 0x1B
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO27 0x1C
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO28 0x1D
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO29 0x1E
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO30 0x1F
+ #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO31 0x20
+ /* Define for GPIO mapping of QSFP Reset signal */
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_MASK 0xFF000000
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_OFFSET 24
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_NA 0x0
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO0 0x1
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO1 0x2
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO2 0x3
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO3 0x4
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO4 0x5
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO5 0x6
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO6 0x7
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO7 0x8
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO8 0x9
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO9 0xA
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO10 0xB
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO11 0xC
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO12 0xD
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO13 0xE
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO14 0xF
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO15 0x10
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO16 0x11
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO17 0x12
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO18 0x13
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO19 0x14
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO20 0x15
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO21 0x16
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO22 0x17
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO23 0x18
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO24 0x19
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO25 0x1A
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO26 0x1B
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO27 0x1C
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO28 0x1D
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO29 0x1E
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO30 0x1F
+ #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO31 0x20
+ u32 port_generic_cont_02; /* 0x9C */
+ /* Define for GPIO mapping of QSFP Transceiver LP mode */
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_MASK 0x000000FF
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_OFFSET 0
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_NA 0x0
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO0 0x1
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO1 0x2
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO2 0x3
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO3 0x4
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO4 0x5
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO5 0x6
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO6 0x7
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO7 0x8
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO8 0x9
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO9 0xA
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO10 0xB
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO11 0xC
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO12 0xD
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO13 0xE
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO14 0xF
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO15 0x10
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO16 0x11
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO17 0x12
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO18 0x13
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO19 0x14
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO20 0x15
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO21 0x16
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO22 0x17
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO23 0x18
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO24 0x19
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO25 0x1A
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO26 0x1B
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO27 0x1C
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO28 0x1D
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO29 0x1E
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO30 0x1F
+ #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO31 0x20
+ /* Define for GPIO mapping of Transceiver Power Enable */
+ #define NVM_CFG1_PORT_MODULE_POWER_MASK 0x0000FF00
+ #define NVM_CFG1_PORT_MODULE_POWER_OFFSET 8
+ #define NVM_CFG1_PORT_MODULE_POWER_NA 0x0
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO0 0x1
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO1 0x2
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO2 0x3
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO3 0x4
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO4 0x5
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO5 0x6
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO6 0x7
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO7 0x8
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO8 0x9
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO9 0xA
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO10 0xB
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO11 0xC
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO12 0xD
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO13 0xE
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO14 0xF
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO15 0x10
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO16 0x11
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO17 0x12
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO18 0x13
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO19 0x14
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO20 0x15
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO21 0x16
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO22 0x17
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO23 0x18
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO24 0x19
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO25 0x1A
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO26 0x1B
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO27 0x1C
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO28 0x1D
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO29 0x1E
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO30 0x1F
+ #define NVM_CFG1_PORT_MODULE_POWER_GPIO31 0x20
+ /* Define for LASI Mapping of Interrupt from module or PHY */
+ #define NVM_CFG1_PORT_LASI_INTR_IN_MASK 0x000F0000
+ #define NVM_CFG1_PORT_LASI_INTR_IN_OFFSET 16
+ #define NVM_CFG1_PORT_LASI_INTR_IN_NA 0x0
+ #define NVM_CFG1_PORT_LASI_INTR_IN_LASI0 0x1
+ #define NVM_CFG1_PORT_LASI_INTR_IN_LASI1 0x2
+ #define NVM_CFG1_PORT_LASI_INTR_IN_LASI2 0x3
+ #define NVM_CFG1_PORT_LASI_INTR_IN_LASI3 0x4
+ u32 reserved[110]; /* 0xA0 */