-#define NWM_REG_MAC0_K2_E5 0x800400UL
-#define CNIG_REG_NIG_PORT0_CONF_K2_E5 0x218200UL
-#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT 0
-#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT 1
-#define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT 3
-#define ETH_MAC_REG_XIF_MODE_K2_E5 0x000080UL
-#define ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT 0
-#define ETH_MAC_REG_FRM_LENGTH_K2_E5 0x000014UL
-#define ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT 0
-#define ETH_MAC_REG_TX_IPG_LENGTH_K2_E5 0x000044UL
-#define ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT 0
-#define ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5 0x00001cUL
-#define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT 0
-#define ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5 0x000020UL
-#define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT 16
-#define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT 0
-#define ETH_MAC_REG_COMMAND_CONFIG_K2_E5 0x000008UL
+#define NWM_REG_MAC0_K2 0x800400UL
+ #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_SHIFT 0
+ #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_SHIFT 1
+ #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_SHIFT 3
+#define ETH_MAC_REG_XIF_MODE_K2 0x000080UL
+ #define ETH_MAC_REG_XIF_MODE_XGMII_K2_SHIFT 0
+#define ETH_MAC_REG_FRM_LENGTH_K2 0x000014UL
+ #define ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_SHIFT 0
+#define ETH_MAC_REG_TX_IPG_LENGTH_K2 0x000044UL
+ #define ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_SHIFT 0
+#define ETH_MAC_REG_RX_FIFO_SECTIONS_K2 0x00001cUL
+ #define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_SHIFT 0
+#define ETH_MAC_REG_TX_FIFO_SECTIONS_K2 0x000020UL
+ #define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_SHIFT 16
+ #define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_SHIFT 0
+ #define ETH_MAC_REG_COMMAND_CONFIG_CRC_FWD_K2 (0x1 << 6)
+ #define ETH_MAC_REG_COMMAND_CONFIG_CRC_FWD_K2_SHIFT 6
+#define ETH_MAC_REG_COMMAND_CONFIG_K2 0x000008UL